Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test

This paper presents the results of resistive-open defect insertion in different locations of Infineon 0.13 μm embedded-SRAM with the main purpose of verifying the presence of dynamic faults. This study is based on the injection of resistive defects as their presence in VDSM technologies is more and more frequent. Electrical simulations have been performed to evaluate the effects of those defects in terms of detected functional faults. Read destructive, deceptive read destructive and dynamic read destructive faults have been reproduced and accurately characterized. The dependence of the fault detection has been put in relation with memory operating conditions, resistance value and clock cycle, and the importance of at speed testing for dynamic fault models has been pointed out. Finally resistive Address Decoder Open Faults (ADOF) have been simulated and the conditions that maximize the fault detection have been discussed as well as the resulting implications for memory test.

[1]  Zaid Al-Ars,et al.  Functional memory faults: a formal notation and a taxonomy , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[2]  Keith Baker,et al.  Defect-based delay testing of resistive vias-contacts a critical evaluation , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[3]  Manoj Sachdev.  Open Defects in CMOS RAM Address Decoders , 1997, IEEE Des. Test Comput..

[4]  G L MADDOX,et al.  A critical evaluation , 2012 .

[5]  Edward J. McCluskey,et al.  Testing for resistive opens and stuck opens , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[6]  Ad J. van de Goor,et al.  Industrial evaluation of stress combinations for march tests applied to SRAMs , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[7]  Kamran Zarrineh,et al.  Defect analysis and realistic fault model extensions for static random access memories , 2000, Records of the IEEE International Workshop on Memory Technology, Design and Testing.

[8]  Arnaud Virazel,et al.  Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution , 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..

[9]  E. S. Cooley,et al.  False write through and un-restored write electrical level fault models for SRAMs , 1997, Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. NO.97TB100159).

[10]  Arnaud Virazel,et al.  March iC-: an improved version of March C- for ADOFs detection , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

[11]  Ad J. van de Goor,et al.  Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[12]  Ad J. van de Goor,et al.  Using March Tests to Test SRAMs , 1993, IEEE Des. Test Comput..

[13]  T. W. Williams,et al.  Detection of CMOS address decoder open faults with March and pseudo random memory tests , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[14]  A. J. van de Goor,et al.  Testing Semiconductor Memories: Theory and Practice , 1998 .

[15]  Wayne M. Needham,et al.  High volume microprocessor test escapes, an analysis of defects our tests are missing , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[16]  Arnaud Virazel,et al.  March Tests Improvements for Address Decoder Open and Resistive Open Fault Detection , 2004 .

[17]  C. Delporte.  Habilitation à diriger des recherches , 2003 .

[18]  Rosa Rodríguez-Montañés,et al.  Resistance characterization for weak open defects , 2002, IEEE Design & Test of Computers.

[19]  Said Hamdioui,et al.  Testing static and dynamic faults in random access memories , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

[20]  J. Otterstedt,et al.  Integration of non-classical faults in standard March tests , 1998, Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236).

[21]  Marian Marinescu,et al.  Simple and Efficient Algorithms for Functional RAM Testing , 1982, ITC.

[22]  A. van de Goor.  An industrial evaluation of DRAM tests , 2004, IEEE Design & Test of Computers.

[23]  Manoj Sachdev.  Test and testability techniques for open defects in RAM address decoders , 1996, Proceedings ED&TC European Design and Test Conference.