AOXMIN-MV: A Heuristic Algorithm for AND-OR-XOR Minimization

Three-level logic is shown to have a potential for reduction of the area over twolevel implementations, as well as for a gain in speed over multi-level implementations. In this paper we present an heuristic algorithm, AOXMIN-MV, targeting a three-level logic expression which is an XOR of two sum-of-products. For some practical functions, such an AND-OR-XOR expression may have up to 60 times less product-terms compared to the classical sum-of-products form. Several algorithms for finding minimal AND-OR-XOR expressions were presented, but they all are time-consuming for large functions. The algorithm presented here solves this problem by (1) introducing an estimation metric, checking whether the input function is likely to have a compact AND-OR-XOR expression; (2) employing a new strategy for decomposing the input function into two sum-of-products; (3) treating the output part of a multiple-output function as a single multiple-valued variable. The experimental results show that these modification yield a faster and more efficient algorithm. Furthermore, it gives a solution to a more general problem of minimization of multiple-valued input binary-valued output logic functions.

[1]  R. M. Mattheyses,et al.  A Linear-Time Heuristic for Improving Network Partitions , 1982, 19th Design Automation Conference.

[2]  Tsutomu Sasao An application of multiple-valued logic to a design of programmable logic arrays , 1978, MVL '78.

[3]  Daniel D. Gajski,et al.  High ― Level Synthesis: Introduction to Chip and System Design , 1992 .

[4]  Tsutomu Sasao A Design Method for AND-OR-EXOR Three-Level Networks , 1995 .

[5]  D. Michael Miller Multiple-valued logic design tools , 1993, [1993] Proceedings of the Twenty-Third International Symposium on Multiple-Valued Logic.

[6]  Robert K. Brayton,et al.  Sequential circuit design using synthesis and optimization , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[7]  Tsutomu Sasao,et al.  On the Complexity of Three-Level Logic Circuits(Complexity Theory and Related Topics) , 1990 .

[8]  D. M. Miller,et al.  Upper bound on number of products in AND-OR-XOR expansion of logic functions , 1995 .

[9]  Tsutomu Sasao,et al.  A heuristic algorithm to design AND-OR-EXOR three-level networks , 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.

[10]  Robert K. Brayton,et al.  Logic Minimization Algorithms for VLSI Synthesis , 1984, The Kluwer International Series in Engineering and Computer Science.

[11]  Charles M. Fiduccia,et al.  A linear-time heuristic for improving network partitions , 1988, 25 years of DAC.

[12]  Alberto L. Sangiovanni-Vincentelli,et al.  Multiple-Valued Minimization for PLA Optimization , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[14]  Robert K. Brayton,et al.  Three-level decomposition with application to PLDs , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[15]  Robert Tibshirani,et al.  An Introduction to the Bootstrap , 1994 .

[16]  Elena Dubrova,et al.  AOXMIN: A Three-Level Heuristic AND-OR-XOR Minimizer for Boolean Functions , 1997 .