Subthreshold leakage power reduction in VLSI circuits: A survey

As technology enters into deep submicron regime, subthreshold leakage power increases exponentially and become a limiting factor in the performance of portable and battery operated electronic devices. To increase the life of battery and computational capacities of portable devices the reduction of power in standby/ sleep mode is evident. Now a day's power dissipation emerged as a major design constraint in the device miniaturization and integration of huge number of transistors. A detailed survey of alternative techniques to reduce subthreshold leakage power is presented in this paper.

[1]  A. Tajalli,et al.  Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications , 2008, IEEE Journal of Solid-State Circuits.

[2]  Masashi Horiguchi,et al.  Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's , 1993 .

[3]  Jun-Cheol Park,et al.  Sleepy Stack Leakage Reduction , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Yusuf Leblebici,et al.  Leakage Current Reduction Using Subthreshold Source-Coupled Logic , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

[5]  M. Aoki,et al.  Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs) , 1993 .

[6]  Takayasu Sakurai,et al.  VTCMOS characteristics and its optimum conditions predicted by a compact analytical model , 2001, ISLPED '01.

[7]  Vincent John Mooney,et al.  Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design , 2006, 2006 IFIP International Conference on Very Large Scale Integration.

[8]  James Tschanz,et al.  Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors , 2002, DAC '02.

[9]  Armin Tajalli,et al.  Leakage Current Reduction Using Subthreshold Source-Coupled Logic , 2009 .

[10]  Kazuo Yano,et al.  Random Modulation: Multi-Threshold-Voltage Design Methodology in Sub-2-V Power Supply CMOS , 2000 .

[11]  Gaurav Saini,et al.  Stacked keeper with body bias: A new approach to reduce leakage power for low power VLSI design , 2014, 2014 IEEE International Conference on Advanced Communications, Control and Computing Technologies.

[12]  T. Sakurai,et al.  A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current , 2000, IEEE Journal of Solid-State Circuits.

[13]  N. Ranganathan,et al.  LECTOR: a technique for leakage reduction in CMOS circuits , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[14]  M. S. Islam,et al.  Dual stack method: A novel approach to low leakage and speed power product VLSI design , 2010, International Conference on Electrical & Computer Engineering (ICECE 2010).

[15]  A. Chandrakasan,et al.  MTCMOS sequential circuits , 2001, Proceedings of the 27th European Solid-State Circuits Conference.

[16]  Sayed Masoud Sayedi,et al.  Low-power state-retention dual edge-triggered pulsed latch , 2010, 2010 18th Iranian Conference on Electrical Engineering.

[17]  Massoud Pedram,et al.  Leakage current reduction in CMOS VLSI circuits by input vector control , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[18]  Dhireesha Kudithipudi,et al.  GALEOR: Leakage reduction for CMOS circuits , 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

[19]  Preetham Lakshmikanthan,et al.  VCLEARIT: a VLSI CMOS circuit leakage reduction technique for nanoscale technologies , 2007, CARN.

[20]  Shin'ichiro Mutoh,et al.  1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS , 1995, IEEE J. Solid State Circuits.

[21]  Narayanan Vijaykrishnan,et al.  Implications of technology scaling on leakage reduction techniques , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[22]  Armin Tajalli,et al.  Ultra-low power subthreshold current-mode logic utilising PMOS load device , 2007 .