Minimizing leakage power of sequential circuits through mixed-Vt flip-flops and multi-Vt combinational gates

The current use of multi-<i>V<sub>t</sub></i> to control leakage power targets combinational gates, even though sequential elements such as flip-flops and latches also contribute appreciable leakage. We can, nevertheless, apply multi-<i>V<sub>t</sub></i> to flip-flops, but few can take advantage of high-<i>V<sub>t</sub></i>, which causes abrupt changes in timing. We combine low- and high-<i>V<sub>t</sub></i> at the transistor level to design mixed-<i>V<sub>t</sub></i> flip-flops with reduced leakage, an unchanged footprint, and a small increase in either setup time or clock-to-Q delay, but not both. An allocation algorithm for two <i>V<sub>t</sub></i>s determines the <i>V<sub>t</sub></i> (mixed, high, or low) of each flip-flop and the <i>V<sub>t</sub></i> of each combinational gate (high or low) in a sequential circuit. Experiments with 65-nm technology show an average leakage saving of 42% compared to conventional multi-<i>V<sub>t</sub></i> approaches; the leakage of flip-flops alone is cut by 78%. This saving is largely unaffected by die-to-die or within-die process variations, which we show through simulations. Standard deviation of leakage caused by process variation is also reduced due to less use of low-<i>V<sub>t</sub></i> devices. We also extend our approach to three <i>V<sub>t</sub></i>s, and obtain a further 14% reduction in leakage.

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