500-㎒부터 1.2-㎓까지의 동작 주파수에서 일정한 루프 대역폭을 갖는 메모리 컨트롤러 PLL

A phase-locked loop(PLL) circuit with a constant loop bandwidth and low supply-noise sensitivity was implemented in a 0.13㎛ CMOS process for a high-speed memory controller. A charge pump with current-mismatch calibration reduces the channel length modulation effect by the output voltage variation. In order to improve PSRR of the PLL, a current-controlled oscillator is adopted instead of voltage-controlled oscillator. With these circuits, the implemented PLL features a constant loop bandwidth of 4㎒ and a low power supply noise sensitivity in an operating frequency ranging from 500㎒ to 1.2㎓. To verify the effectiveness of the proposed PLL, the power-management IC (PMIC) output fluctuation and SSN noise is modeled. The simulation result shows that the rms jitter is reduced from 79.23 ps to 19.93 ps.