论文信息 - Increasing substrate resistance to improve the turn-on uniformity of a high-voltage multi-finger GG-nLDMOS

Increasing substrate resistance to improve the turn-on uniformity of a high-voltage multi-finger GG-nLDMOS

With the impact of the non-uniform turn-on phenomenon, the ESD robustness of high-voltage multi- finger devices is limited. This paper describes the operational mechanism of a GG-nLDMOS device under ESD stress conditions and analyzes the reason that causes the non-uniform turn-on characteristics of a multi-finger GG- nLDMOS device. By means of increasing substrate resistance, an optimized device structure is proposed to improve the turn-on uniformity of a high-voltage multi-finger GG-nLDMOS. This approach has been successfully verified in a 0.35 m 40 V BCD process. The TLP test results reveal that increasing the substrate resistance can effectively enhance the turn-on uniformity of the 40 V multi-finger GG-nLDMOS device and improve its ESD robustness.

He Chuan | Zhang Bo | Jiang Lingli | Fan Hang

[1] Tung-Yang Chen,et al. Investigation of the gate-driven effect and substrate-triggered effect on ESD robustness of CMOS devices , 2001 .

[2] E. Nowak,et al. Process and design for ESD robustness in deep submicron CMOS technology , 1996, Proceedings of International Reliability Physics Symposium.

[3] Jian-Hsing Lee,et al. A Simple and Useful Layout Scheme to Achieve Uniform Current Distribution for Multi-Finger Silicided Grounded-Gate NMOS , 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.

[4] Amitava Chatterjee,et al. Improving the ESD failure threshold of silicided n-MOS output transistors by ensuring uniform current flow , 1992 .

[5] G. Groeseneken,et al. Non-uniform triggering of gg-nMOSt investigated by combined emission microscopy and transmission line pulsing , 1998, Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347).

[6] Tung-Yang Chen,et al. Substrate-triggered technique for on-chip ESD protection design in a 0.18-/spl mu/m salicided CMOS process , 2003 .

[7] Kaustav Banerjee,et al. Analysis of nonuniform ESD current distribution in deep submicron NMOS transistors , 2002 .

[8] Tetsuro Hirano,et al. Source engineering for ESD robust NLDMOS , 2011, EOS/ESD Symposium Proceedings.