High Speed and Pipelined Analog to DigitalConverter for Multiple Processor System onChip

This paper presents the high speed and high resolution analog to digital conversion using successive approximation registers (SAR) with split DAC structure based on combining three ADC architectures namely split type SAR, Sigma-Delta and flash type ADC using pipelining method. The static linearity performance of this approach is based on integrating parallelism and pipelining method in SAR with reconfigurable sampling rate to maintain the tradeoff between speed, accuracy, resolution and architectural complexity. Gaussian smoothing function is introduced to improve the linearity and to remove glitches. This architecture flexibility provides higher resolution and high speed Performance is demonstrated and verified by behavioral simulations using Modelsim 6.4a. Measurement results of power, speed, and linearity of this approach are measured through Quartus II 9.0 IDE that clearly shows the benefits of hybrid SAR ADC in terms of area complexity and speed.