In-growth test for monolithic 3D integrated SRAM

Monolithic three-dimensional integration (M3I) directly fabricates tiers of integrated circuits upon each other and provides millions of vertical interconnections with inter-layer vias (ILVs). It thus brings higher integration density and communication capability compared with three-dimensional stacked integration (3D-SI). However, the Known-Good-Die problem haunting 3D-SI-a faulty tier causes the failure of the entire stack-also occurs in M3I. Lack of efficient test methodologies such as the pre-bond testing in 3D-SI, M3I may have a more significant yield drop and thus its cost may be unacceptable for main-stream adoption. This paper introduces a novel In-growth test method for M3I SRAM. We propose a novel Design-for-Test (DfT) methodology to enable the proposed In-growth test on cell-level partitioned incomplete SRAM cells. We also build a statistical model of cost and discover a prospective judgement to determine whether or not to stop the fabrication, in order to prevent from raising the cost of fabricating more tiers upon the irreparable tiers. We find that a “sweet point” exists in the judgement, which can minimize the overall cost. Experimental results show the effectiveness of our proposed test methodology.

[1]  Hai Wei,et al.  Monolithic 3D integration advances and challenges: From technology to system levels , 2014, 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

[2]  Yan Han,et al.  Fault clustering technique for 3D memory BISR , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

[3]  A. Toffoli,et al.  Advances in 3D CMOS sequential integration , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[4]  Israel Koren,et al.  Defect tolerance in VLSI circuits: techniques and yield analysis , 1998, Proc. IEEE.

[5]  Hsien-Hsin S. Lee,et al.  Test Challenges for 3D Integrated Circuits , 2009, IEEE Design & Test of Computers.

[6]  Hsien-Hsin S. Lee,et al.  Pre-bond testable low-power clock tree design for 3D stacked ICs , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[7]  C. Chuang,et al.  Evaluation of Monolithic 3-D Logic Circuits and 6T SRAMs With InGaAs-n/Ge-p Ultra-Thin-Body MOSFETs , 2016, IEEE Journal of the Electron Devices Society.

[8]  Sung Kyu Lim,et al.  Ultra-high density 3D SRAM cell designs for monolithic 3D integration , 2012, 2012 IEEE International Interconnect Technology Conference.

[9]  Ad J. van de Goor,et al.  March tests for word-oriented memories , 1998, Proceedings Design, Automation and Test in Europe.