A Communication-Aware Topological Mapping Technique for NoCs

Networks---on---Chip (NoCs) have been proposed as a promising solution to the complex on-chip communication problems derived from the increasing number of processor cores. The design of NoCs involves several key issues, being the topological mapping (the mapping of the Intellectual Properties (IPs) to network nodes) one of them. Several proposals have been focused on topological mapping last years, but they require the experimental validation of each mapping considered. In this paper, we propose a communication-aware topological mapping technique for NoCs. This technique is based on the experimental correlation of the network model with the actual network performance, thus avoiding the need to experimentally evaluate each mapping explored. The evaluation results show that the proposed technique can provide better performance than the currently existing techniques (in terms of both network latency and energy consumption). Additionally, it can be used for both regular and irregular topologies.