Hardware implementation of a practical complexity Spectrally Efficient FDM reconfigurable receiver

Spectrally Efficient Frequency Division Multiplexing (SEFDM) systems offer significant bandwidth gains at the expense of receiver complexity. While Maximum Likelihood (ML) and Sphere Decoding (SD) yield optimum performance, these techniques suffer from an impractical computational complexity. Previous work has shown that hybrid detectors combining Truncated Singular Value Decomposition (TSVD) with Fixed SD (FSD) offer a targeted reduction in complexity with an acceptable error performance. This work describes a modified FSD adopting a Sort-Free (SF) approach to make the algorithm better-suited for application in the real world. It further presents for the first time the hardware implementation of a TSVD-FSD using Field Programmable Gate Arrays (FPGAs) and Digital Signal Processors (DSPs). The TSVD detector is realized on an FPGA with a flexible and reconfigurable design supporting different system sizes, modulation orders and levels of bandwidth compression while providing a data rate of up to 136.8 Mbps. The modified FSD is implemented on a DSP and is shown to provide up to six times greater speed when compared to the conventional FSD. The error performance, computational complexity and resource utilization of the system are examined.

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