Hardware Reduction for Mealy UFSMs

The Chapter deals with optimization of logic circuits of hybrid FPGA-based Mealy FSMs. First of all, the models with two state registers are discussed. This approach allows removal of direct dependence among logical conditions and output functions of Mealy FSM. Next, the proposed design methods are presented. Some improvements are proposed for further hardware reduction. They are based on the special state assignment and transformation of state codes. The proposed methods target joint using such blocks as LUTs, PLAs and EMBs in FSM circuits. The models are discussed based on the principle of object transformation. The last part of the chapter is connected with design methods connected with the object transformation.