An RNS Architecture for Quasi-Chaotic Oscillators

Wideband chaotic carrier is a promising solution for wideband communication, since it overcomes the disadvantages of both narrowband and spread-spectrum communication. It is particularly suited to realize information encryption for secure communication. Chaotic signals can be generated by using discrete-time non-linear dynamical circuits, since they can exhibit a quasi-chaotic (QC) behavior. A particular implementation of QC digital filters can be based on finite precision arithmetic and, in particular, on residue number system (RNS) circuits, which possess very attractive features with regard to their VLSI implementation. In the present paper, we propose an RNS architecture that can be used in connection with secure communication. Each RNS channel consists of a QC oscillator, having its coefficients belonging to a Galois field defined by a prime modulus. In particular, the QC behavior is ensured by well-known properties of primitive polynomials in this field, which generate the characteristic feedback of the oscillator. We demonstrate in the paper that the proposed RNS architecture yields a cost-effective VLSI implementation, which favorably compares with respect to other secure communication approaches proposed in the technical literature. We obtain encouraging results both in terms of confidentiality of the encrypted information and of throughput rate for real-time applications. Moreover, we propose an extended architecture suited to the protection of the secure communication system against transmission errors, by using the self-correcting ability of Redundant RNS (RRNS).

[1]  Jr. W.A. Chren,et al.  One-hot residue coding for low delay-power product CMOS design , 1998 .

[2]  Massimo Panella,et al.  RNS quasi-chaotic generator for self-correcting secure communication , 2001 .

[3]  Michael A. Soderstrand,et al.  Multipliers for residue-number-arithmetic digital filters , 1977 .

[4]  Francesco Piazza,et al.  A Systolic Redundant Residue Arithmetic Error Correction Circuit , 1993, IEEE Trans. Computers.

[5]  Massimo Panella,et al.  RNS quasi-chaotic generators , 2000 .

[6]  T. Marshall,et al.  Coding of Real-Number Sequences for Error Correction: A Digital Signal Processing Problem , 1984, IEEE J. Sel. Areas Commun..

[7]  K. Kelber,et al.  Discrete-time chaotic encryption systems. III. Cryptographical analysis , 1998 .

[8]  Vassilis Paliouras,et al.  Novel high-radix residue number system architectures , 2000 .

[9]  Solomon W. Golomb,et al.  Shift Register Sequences , 1981 .

[10]  Francesco Piazza,et al.  Fast Combinatorial RNS Processors for DSP Applications , 1995, IEEE Trans. Computers.

[11]  Vassilis Paliouras,et al.  Multifunction architectures for RNS processors , 1999 .

[12]  Alan V. Oppenheim,et al.  Discrete-Time Signal Pro-cessing , 1989 .

[13]  W. K. Jenkins,et al.  Self-checking properties of residue number error checkers based on mixed radix conversion , 1988 .

[14]  Gian Carlo Cardarilli,et al.  Properties and synthesis of RNS digital circuits , 1990 .

[15]  L. Chua,et al.  On chaos of digital filters in the real world , 1991 .

[16]  C. D. Walter,et al.  Systolic Modular Multiplication , 1993, IEEE Trans. Computers.

[17]  M. Gotz,et al.  Discrete-time chaotic encryption systems. I. Statistical design approach , 1997 .

[18]  Riccardo Rovatti,et al.  Chaotic complex spreading sequences for asynchronous DS-CDMA. I. System modeling and results , 1997 .

[19]  I. Vinogradov,et al.  Elements of number theory , 1954 .

[20]  Gianluca Mazzini DS-CDMA systems using q-level m sequences: coding map theory , 1997, IEEE Trans. Commun..

[21]  D. R. Frey,et al.  Chaotic digital encoding: an approach to secure communication , 1993 .

[22]  Philippe Bouysse,et al.  DSP implementation of self-synchronised chaotic encoder-decoder , 2000 .

[23]  John J. Komo,et al.  Primitive polynomials and M-sequences over GF(qm) , 1993, IEEE Trans. Inf. Theory.

[24]  Alberto Tesi,et al.  Dead-beat chaos synchronization in discrete-time systems , 1995 .

[25]  Michael Peter Kennedy,et al.  The role of synchronization in digital communications using chaos. I . Fundamentals of digital communications , 1997 .

[26]  Vassilis Paliouras,et al.  Area-time performance of VLSI FIR filter architectures based on residue arithmetic , 1997, EUROMICRO 97. Proceedings of the 23rd EUROMICRO Conference: New Frontiers of Information Technology (Cat. No.97TB100167).

[27]  William J. Park,et al.  Relationships between m -sequences over GF(q) and GF(qm) , 1989, IEEE Trans. Inf. Theory.

[28]  David Mandelbaum MANDELBAUM : ERROR CORRECTION IN RESIDUE ARITHMETIC , 2022 .

[29]  D. Radhakrishnan,et al.  Novel approaches to the design of VLSI RNS multipliers , 1992 .

[30]  R. Blahut Theory and practice of error control codes , 1983 .

[31]  Harald Niederreiter,et al.  Introduction to finite fields and their applications: List of Symbols , 1986 .

[32]  Shinji Nakamura,et al.  A Single Chip Parallel Multiplier by MOS Technology , 1988, IEEE Trans. Computers.

[33]  K. Elleithy,et al.  Fast and flexible architectures for RNS arithmetic decoding , 1992 .