Instruction-Level Parallelism for Reconfigurable Computing

Reconfigurable coprocessors can exploit large degrees of instruction-level parallelism (ILP). In compiling sequential code for reconfigurable coprocessors, we have found it convenient to borrow techniques previously developed for exploiting ILP for very long instruction word (VLIW) processors. With some minor adaptations, these techniques are a natural match for automatic compilation to a reconfigurable coprocessor. This paper will review these techniques in their original context, describe how we have adapted them for reconfigurable computing, and present some preliminary results on compiling application programs written in the C programming language.

[1]  John Wawrzynek,et al.  Garp: a MIPS processor with a reconfigurable coprocessor , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[2]  S. Ghosh,et al.  An asynchronous approach to efficient execution of programs on adaptive architectures utilizing FPGAs , 1994, Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines.

[3]  Niklaus Wirth.  Hardware Compilation: Translating Programs into Circuits , 1998, Computer.

[4]  John R. Ellis,et al.  Bulldog: A Compiler for VLIW Architectures , 1986 .

[5]  Brad Hutchings,et al.  Density enhancement of a neural network using FPGAs and run-time reconfiguration , 1994, Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines.

[6]  Scott A. Mahlke,et al.  A comparison of full and partial predicated execution support for ILP processors , 1995, Proceedings 22nd Annual International Symposium on Computer Architecture.

[7]  Scott Mahlke,et al.  Effective compiler support for predicated execution using the hyperblock , 1992, MICRO 1992.

[8]  J A Fisher,et al.  Instruction-Level Parallel Processing , 1991, Science.

[9]  André DeHon,et al.  DPGA-coupled microprocessors: commodity ICs for the early 21st Century , 1994, Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines.

[10]  M. J. Gonzalez,et al.  A data-parallel programming model for reconfigurable architectures , 1993, [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines.

[11]  Gerald J. Holloway,et al.  The flow analysis and transformation libraries of Machine SUIF , 1997 .

[12]  Scott A. Mahlke,et al.  Effective compiler support for predicated execution using the hyperblock , 1992, MICRO 25.

[13]  Monica S. Lam,et al.  Maximizing Multiprocessor Performance with the SUIF Compiler , 1996, Digit. Tech. J..