VLSI implementation of modulo multiplication using carry free addition

In this paper we show how the technique of carry free addition can be used to get efficient algorithms for modulo multiplication. We present two algorithms and their VLSI implementations. The first algorithm runs in time O(nlogn) (for n bit numbers), has an AT/sup 2/ measure of O((nlogn)/sup 3/), and can be implemented using a systolic architecture. The second algorithm is a parallel modulo algorithm that uses table look up to speed up computation. The time complexity is O(logn), the AT/sup 2/ measure is O((n logn)/sup 2/), and it can also be implemented using a systolic architecture. Used with a O(logn) multiplier, it can perform module multiplication in O(logn) time. Both the algorithms have the advantage that the circuit is independent of the modulus N. Thus the same chip can be used for RSA cryptosystems with different moduli.

[1]  A. J. Atrubin.  A One-Dimensional Real-Time Iterative Multiplier , 1965, IEEE Trans. Electron. Comput..

[2]  Shuzo Yajima,et al.  Modular Multiplication Hardware Algorithms with a Redundant Representation and Their Application to RSA Cryptosystem , 1992, IEEE Trans. Computers.

[3]  Ted Herman.  Linear Algorithms That Are Efficiently Parallelized to Time O(logn) , 1985 .

[4]  Shimon Even.  Systolic Modular Multiplication , 1990, CRYPTO.

[5]  Hikaru Morita,et al.  A Fast Modular-multiplication Algorithm based on a Higher Radix , 1989, CRYPTO.

[6]  Adi Shamir,et al.  A method for obtaining digital signatures and public-key cryptosystems , 1978, CACM.

[7]  Pradip K. Srimani,et al.  Fast Parallel Algorithms for Binary Multiplication and Their Implementation on Systolic Architectures , 1989, IEEE Trans. Computers.

[8]  Ernest F. Brickell,et al.  A Survey of Hardware Implementation of RSA (Abstract) , 1989, CRYPTO.

[9]  Whitfield Diffie,et al.  New Directions in Cryptography , 1976, IEEE Trans. Inf. Theory.

[10]  R L Rivest,et al.  Factoring and cryptography. , 1988, Science.

[11]  Ernest A. Brickell.  A survey of hardware implementations of RSA (abstract) , 1989, CRYPTO 1989.

[12]  Paul A. Findlay,et al.  Modular Exponentiation Using Recursive Sums of Residues , 1989, CRYPTO.

[13]  Hiroto Yasuura,et al.  High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree , 1985, IEEE Transactions on Computers.

[14]  I-Ngo Chen,et al.  An algorithm for modular exponentiation , 1981, 1981 IEEE 5th Symposium on Computer Arithmetic (ARITH).

[15]  Donald Ervin Knuth,et al.  The Art of Computer Programming , 1968 .