Techniques for aggressive supply voltage scaling and efficient regulation [CMOS digital circuits]
暂无分享,去创建一个
[1] Hiroaki Misawa,et al. Data-dependent logic swing internal bus architecture for ultralow-power lsi's. ieee j. solid-state , 1995 .
[2] Mani B. Srivastava,et al. Predictive system shutdown and other architectural techniques for energy efficient programmable computation , 1996, IEEE Trans. Very Large Scale Integr. Syst..
[3] 藤田 哲也,et al. A 0.9V 150MHz 10mW 4mm^2 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme , 1996 .
[4] Scott Shenker,et al. Scheduling for reduced CPU energy , 1994, OSDI '94.
[5] K. Itoh,et al. Subthreshold-current reduction circuits for multi-gigabit DRAM's , 1993, Symposium 1993 on VLSI Circuits.
[6] L. S. Nielsen,et al. Low-power operation using self-timed circuits and adaptive scaling of the supply voltage , 1994, IEEE Trans. Very Large Scale Integr. Syst..
[7] Kiyoo Itoh,et al. Sub-1-V swing internal bus architecture for future low-power ULSIs , 1993 .
[8] A. Chandrakasan,et al. An efficient controller for variable supply-voltage low power processing , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.
[9] P. Balsara,et al. Delay balanced multipliers for low power/low voltage DSP core , 1995, 1995 IEEE Symposium on Low Power Electronics. Digest of Technical Papers.
[10] Shin'ichiro Mutoh,et al. 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS , 1995, IEEE J. Solid State Circuits.
[11] Mark Horowitz,et al. A low power switching power supply for self-clocked systems , 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.
[12] Abram P. Dancy. Power supplies for ultra low power applications , 1996 .
[13] A voltage reduction technique for digital systems , 1990, 1990 37th IEEE International Conference on Solid-State Circuits.
[14] Anantha P. Chandrakasan,et al. Low Power Digital CMOS Design , 1995 .
[15] Dimitri A. Antoniadis,et al. Back gated CMOS on SOIAS for dynamic threshold voltage control , 1995, Proceedings of International Electron Devices Meeting.
[16] Robert W. Brodersen,et al. A low-voltage CMOS DC-DC converter for a portable battery-operated system , 1994, Proceedings of 1994 Power Electronics Specialist Conference - PESC'94.
[17] Hendrikus J. M. Veendrick,et al. Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits , 1984 .
[18] J. Burr. WP 5.2: A 200mV Self-Testing EncoderlDecoder using Stanford Ultra-Low-Power CMOS , 1974 .
[19] T. Fujita,et al. A 0.9 V 150 MHz 10 mW 4 mm/sup 2/ 2-D discrete cosine transform core processor with variable-threshold-voltage scheme , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.
[20] J. Shott,et al. A 200 mV self-testing encoder/decoder using Stanford ultra-low-power CMOS , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.