An ultra-compact virtual source FET model for deeply-scaled devices: Parameter extraction and validation for standard cell libraries and digital circuits

In this paper, we present the first validation of the virtual source (VS) charge-based compact model for standard cell libraries and large-scale digital circuits. With only a modest number of physically meaningful parameters, the VS model accounts for the main short-channel effects in nanometer technologies. Using a novel DC and transient parameter extraction methodology, the model is verified with simulated data from a well-characterized, industrial 40-nm bulk silicon model. The VS model is used to fully characterize a standard cell library with timing comparisons showing less than 2.7% error with respect to the industrial design kit. Furthermore, a 1001-stage inverter chain and a 32-bit ripple-carry adder are employed as test cases in a vendor CAD environment to validate the use of the VS model for large-scale digital circuit applications. Parametric Vdd sweeps show that the VS model is also ready for usage in low-power design methodologies. Finally, runtime comparisons have shown that the use of the VS model results in a speedup of about 7.6×.

[1]  Mansun Chan,et al.  A robust and physical BSIM3 non-quasi-static transient and AC small-signal model for circuit simulation , 1998 .

[2]  A. R. Newton,et al.  Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas , 1990 .

[3]  M. Lundstrom,et al.  Essential physics of carrier transport in nanoscale MOSFETs , 2002 .

[4]  Ishiuchi,et al.  Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas , 2004 .

[5]  Changwook Jeong,et al.  On Backscattering and Mobility in Nanoscale Silicon MOSFETs , 2009, IEEE Transactions on Electron Devices.

[6]  Gaetano Palumbo,et al.  An Accurate Ultra-Compact I–V Model for Nanometer MOS Transistors With Applications on Digital Circuits , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

[7]  G. Gildenblat,et al.  PSP: An Advanced Surface-Potential-Based MOSFET Model for Circuit Simulation , 2006, IEEE Transactions on Electron Devices.

[8]  Lan Wei,et al.  Virtual-Source-Based Self-Consistent Current and Charge FET Models: From Ballistic to Drift-Diffusion Velocity-Saturation Operation , 2012, IEEE Transactions on Electron Devices.

[9]  Yu Cao,et al.  New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration , 2006, IEEE Transactions on Electron Devices.

[10]  A. Khakifirooz,et al.  A Simple Semiempirical Short-Channel MOSFET Current–Voltage Model Continuous Across All Regions of Operation and Employing Only Physical Parameters , 2009, IEEE Transactions on Electron Devices.

[11]  Rob A. Rutenbar,et al.  Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS , 2008, Proceedings of the IEEE.

[12]  G. T. Wright,et al.  Threshold modelling of MOSFETs for CAD of CMOS-VLSI , 1985 .