A formal specification language for PLC-based control logic

Formal verification, using model checking tools, is promising in developing (IEC 61131) industrial control logic. Formal verification requires a formal specification of the properties to be verified. Specifications in model checking tools are typically expressed using temporal logic. However, the standard temporal logic dialects are not well suited for control engineers who do rarely have a background within computer science. In this paper a new dialect of linear temporal logic, ST-LTL, is introduced that intends to be easier to use for control engineers than the existing dialects. The relation of ST-LTL compared to existing temporal logic dialects is analyzed.

[1]  Oscar Ljungkrantz,et al.  Practice of Industrial Control Logic Programming using Library Components , 2010 .

[2]  Michael Ward.  Sets, functions, and logic: an introduction to abstract mathematics (3rd edn), by Keith Devlin. Pp. 160. £24.99. 2003. ISBN 1 58488 449 5 (Chapman & Hall/CRC). , 2005, The Mathematical Gazette.

[3]  Thomas Menzel,et al.  Methods and tools to the verification of safety-related control software , 2000, Smc 2000 conference proceedings. 2000 ieee international conference on systems, man and cybernetics. 'cybernetics evolving to systems, humans, organizations, and their complex interactions' (cat. no.0.

[4]  Lothar Litz,et al.  Formal methods in PLC programming , 2000, Smc 2000 conference proceedings. 2000 ieee international conference on systems, man and cybernetics. 'cybernetics evolving to systems, humans, organizations, and their complex interactions' (cat. no.0.

[5]  Philippe Schnoebelen,et al.  Systems and Software Verification, Model-Checking Techniques and Tools , 2001 .

[6]  Philippe Schnoebelen,et al.  Systems and Software Verification , 2001, Springer Berlin Heidelberg.

[7]  Dawn M. Tilbury,et al.  A study of current logic design practices in the automotive manufacturing industry , 2003, Int. J. Hum. Comput. Stud..

[8]  George S. Avrunin,et al.  Patterns in property specifications for finite-state verification , 1999, Proceedings of the 1999 International Conference on Software Engineering (IEEE Cat. No.99CB37002).

[9]  Saharon Shelah,et al.  On the temporal analysis of fairness , 1980, POPL '80.

[10]  Kenneth L. McMillan,et al.  Symbolic model checking: an approach to the state explosion problem , 1992 .

[11]  Moshe Y. Vardi,et al.  Branching vs. Linear Time: Semantical Perspective , 2007, ATVA.

[12]  Moshe Y. Vardi.  Branching vs. Linear Time: Final Showdown , 2001, TACAS.

[13]  Valeriy Vyatkin,et al.  Using Visual Specifications in Verification of Industrial Automation Controllers , 2008, EURASIP J. Embed. Syst..

[14]  Volker Gruhn,et al.  Specification patterns for time-related properties , 2005, 12th International Symposium on Temporal Representation and Reasoning (TIME'05).

[15]  Oscar Ljungkrantz,et al.  Formal Specification and Verification of Industrial Control Logic Components , 2010, IEEE Transactions on Automation Science and Engineering.