Three Reference Currents based 12-bit Binary-Weighted Current Steering DAC

This paper presents 12-bit 80 MS/s binary-weighted current-steering Digital to Analog Converter (DAC) using 130nm CMOS technology for High-speed applications. Three reference currents are used in the proposed structure to reduce area about 1/18 of conventional current-steering DAC. Besides, it uses good matching between the current sources to improve the static performance. Latch sizes have been adjusted in driving circuitry as current is being increases in binary fashion cascaded current source is proposed to improve the overdrive voltage for control the current consumption. It uses a current steering array for small size and high speed. The simulated dynamic results are Effective Number of Bits (ENOB) is 11.97 bits, Signal to Noise Ratio (SNR) is 74.24 dB, and Spurious Free Dynamic Range (SFDR) is 89.22 dB. The simulated Static results shows that Max. Differential Nonlinearity (DNL) is 0.022 LSB and Max. Integral Nonlinearity (INL) is 0.72 LSB. It consumes 5.83 mW with supply voltage of 1.2 V and core area is 0.21 mm2.

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