Data-Driven Clock Gating for Digital Filters

Digital filters implement a continuos computation and therefore generally they do not exhibit any structural idleness. This can prevent the usage of classical low-power optimizations that exploit idleness, such as clock gating. In this work, we propose a data-driven implementation of clock gating for digital filters, which relies on the observation that often times the dynamic range of the inputs uses only a small portion of the bidwith, resulting in most of the higher-order bits of the registers having very low switching activity. When this occurs, unused bits in each filter tap can be clock-gated; since all the gated flip-flops share the same idle condition (i.e., new and currently stored are identical) they can share a single clock gating cell. The number of flip-flops that can be gated with a single cell depends on the tradeoff between the power saved and the performance penalty. This technique has been applied on a digital filter used within an ultra low-power industrial design; comparison with other standard and advanced automatic clock-gating methods highlights the effectiveness of the proposed technique.