Process variation effects on circuit performance: TCAD simulation of 256-Mbit technology [DRAMs]

This paper describes the first study of the complete sequence from process simulation to circuit performance and the corresponding sensitivities for 0.25-/spl mu/m technology. This is made possible by a combination of physically based process models and a systematic calibration involving SIMS, one-dimensional (1-D), and two-dimensional (2-D) device characteristics. Simulated nFET and pFET characteristics match hardware (HW) within 5-10% for both long-channel and nominal length devices. Simulated ring-oscillator performance is in good agreement with HW data. Sensitivities of device characteristics and the inverter gate delay to process variations (within 10%) are quantified. These investigations establish the correlation between process variations and circuit performance.

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