An MTJ‐based non‐volatile flip‐flop for high‐performance SoC
暂无分享,去创建一个
Seong-Ook Jung | Kyungho Ryu | Seung H. Kang | Jisu Kim | Jung Pill Kim | Youngdon Jung | Seung-Hyuk Kang | Kyungho Ryu | Jisu Kim | Seong-ook Jung | Jung Pill Kim | Youngdon Jung
[1] Weisheng Zhao,et al. High Speed, High Stability and Low Power Sensing Amplifier for MTJ/CMOS Hybrid Logic Circuits , 2009, IEEE Transactions on Magnetics.
[2] Steve Ferrera,et al. Reconfigurable magnetoelectronic circuits for threshold logic , 2004, Int. J. Circuit Theory Appl..
[3] Nicholas P. Carter,et al. A magnetoelectronic register file cell for a self‐checkpointing microprocessor , 2007, Int. J. Circuit Theory Appl..
[4] Abdoul Rjoub,et al. Efficient multi‐threshold voltage techniques for minimum leakage current in nanoscale technology , 2011, Int. J. Circuit Theory Appl..
[5] Naoki Kasai,et al. Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs , 2009, IEEE J. Solid State Circuits.
[6] A.P. Chandrakasan,et al. A leakage reduction methodology for distributed MTCMOS , 2004, IEEE Journal of Solid-State Circuits.
[7] E. Belhaire,et al. A non-volatile flip-flop in magnetic FPGA chip , 2006, International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006..
[8] Eric Belhaire,et al. New non‐volatile logic based on spin‐MTJ , 2008 .
[9] Mark C. Johnson,et al. Leakage control with efficient use of transistor stacks in single threshold CMOS , 2002, IEEE Trans. Very Large Scale Integr. Syst..
[10] Jacques-Olivier Klein,et al. Low power, high reliability magnetic flip-flop , 2010 .
[11] Weisheng Zhao,et al. Spin-MTJ based Non-volatile Flip-Flop , 2007, 2007 7th IEEE Conference on Nanotechnology (IEEE NANO).
[12] Arijit Raychowdhury,et al. Modeling and analysis of read (RD) disturb in 1T-1STT MTJ memory bits , 2010, 68th Device Research Conference.
[13] M. Hosomi,et al. A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
[14] Ashutosh Das,et al. A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processors , 1999 .
[15] Joy Laskar,et al. A dynamic timing control technique utilizing time borrowing and clock stretching , 2010, IEEE Custom Integrated Circuits Conference 2010.
[16] Mohamed I. Elmasry,et al. Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies , 2002, IEEE Trans. Very Large Scale Integr. Syst..
[17] Satoshi Shigematsu,et al. A 1-V high-speed MTCMOS circuit scheme for power-down application circuits , 1997, IEEE J. Solid State Circuits.
[18] Seong-Ook Jung,et al. Sensing margin trend with technology scaling in MRAM , 2011, Int. J. Circuit Theory Appl..