On Efficient Message Passing on the Intel SCC

The Single-Chip Cloud Computer (SCC) is an experimental processor created by Intel Labs. Instead of the usual shared memory programming, its design favors message passing over a special shared on-chip memory. However, the design of efficient message passing is still an ongoing research work, because the system differs quite much from traditional hardware. This paper presents design options for message passing protocols on the SCC and discusses some implications.

[1]  Ramesh Subramonian,et al.  LogP: towards a realistic model of parallel computation , 1993, PPOPP '93.

[2]  Thorsten von Eicken,et al.  Low-Latency Communication on the IBM RISC System/6000 SP , 1996, Proceedings of the 1996 ACM/IEEE Conference on Supercomputing.

[3]  Maged M. Michael,et al.  Simple, fast, and practical non-blocking and blocking concurrent queue algorithms , 1996, PODC '96.

[4]  Richard P. Martin,et al.  Assessing Fast Network Interfaces , 1996, IEEE Micro.

[5]  Mitsuhisa Sato,et al.  TACO: prototyping high-level object-oriented programming constructs by means of template based programming techniques , 2001, SIGP.

[6]  Vivek Sarkar,et al.  X10: an object-oriented approach to non-uniform cluster computing , 2005, OOPSLA '05.

[7]  Timothy G. Mattson,et al.  Light-weight communications on Intel's single-chip cloud computer processor , 2011, OPSR.

[8]  William N. Scherer,et al.  Scalable synchronous queues , 2009, Commun. ACM.

[9]  Chris J. Scheiman,et al.  Experience with active messages on the Meiko CS-2 , 1995, Proceedings of 9th International Parallel Processing Symposium.

[10]  Timothy Mattson,et al.  A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[11]  Saurabh Dighe,et al.  The 48-core SCC Processor: the Programmer's View , 2010, 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis.