Bent Routing Pattern for FPGA

Routing architecture design is crucial in the early exploration of FPGA fabrics. In the modern unidirectional routing architectures, the signal passes through a programmable switch while turning into the channel perpendicular to the current one at the intersections, which may lead to excessive turning switches in the routing paths and cause the high latency. Most of the researches focus on the routing topology where the wire segments span in either vertical or horizontal direction. In this paper, we propose the bent routing pattern, where the bent wire segments can span in both vertical and horizontal channels without passing through any turning switch. The bent routing topology is designed to keep the regularity and symmetry, and then evaluated by the enhanced VTR. To optimize the architecture with the bent routing pattern, we develop a stochastic searching method based on the simulated annealing algorithm. The results show that the architecture with the mixture of bent wires and straight wires can achieve 9% shorter critical path delay and 11% area-delay product savings on average compared to the architecture with only straight wires.

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