An efficient mechanism for debugging RTL description
暂无分享,去创建一个
[1] Toshimitsu Masuzawa,et al. A BIST method based on concurrent single-control testability of RTL data paths , 2001, Proceedings 10th Asian Test Symposium.
[2] Yves Le Traon,et al. Towards an automatic diagnosis for high-level design validation , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).
[3] M. Fujita,et al. Multiple error diagnosis based on Xlists , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).
[4] Chien-Nan Jimmy Liu,et al. Effective error diagnosis for RTL designs in HDLs , 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..
[5] Masahiro Fujita,et al. Hierarchical error diagnosis targeting RTL circuits , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.
[6] Toshimitsu Masuzawa,et al. Single-control testability of RTL data paths for BIST , 2000, Proceedings of the Ninth Asian Test Symposium.
[7] Toshimitsu Masuzawa,et al. Design for strong testability of RTL data paths to provide complete fault efficiency , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.
[8] Peter Duzy,et al. The Synthesis Approach to Digital System Design , 1992 .
[9] Thomas Kropf,et al. Efficient design error correction of digital circuits , 2000, Proceedings 2000 International Conference on Computer Design.