Thermal-Power Delivery Network Co-Analysis for Multi-Die Integration

In this paper, we present a thermal-power delivery network (PDN) co-analysis framework to analyze various multi-die integration schemes. In the proposed approach, we capture the interdependencies between temperature distribution of the dice in a package and the supply voltage noise. We use standalone thermal and PDN analyses as references to compare our co-analysis results. Using a multi-die package and a bridge-based 2.5-D package case studies, our analysis shows a 10-12% overestimation in steady-state temperature and power supply noise.

[1]  Eric Beyne,et al.  A Novel Fan-Out Concept for Ultra-High Chip-to-Chip Interconnect Density with 20-µm Pitch , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[2]  Muhannad S. Bakir,et al.  Integrated Thermal and Power Delivery Network Co-Simulation Framework for Single-Die and Multi-Die Assemblies , 2017, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[3]  Thomas E. Sarvey,et al.  Monolithic Integration of a Micropin-Fin Heat Sink in a 28-nm FPGA , 2017, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[4]  Muhannad S. Bakir,et al.  Power Delivery Network Benchmarking for Interposer and Bridge-Chip-Based 2.5-D Integration , 2018, IEEE Electron Device Letters.

[5]  Douglas Yu,et al.  InFO (Wafer Level Integrated Fan-Out) Technology , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

[6]  Jung Ho Ahn,et al.  McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).