Multicore Systems On-Chip: Practical Software/Hardware Design
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[1] Enrico Macii,et al. Designing low-power circuits: practical recipes , 2001 .
[2] Nicola Concer,et al. Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh , 2006, Proceedings of the Design Automation & Test in Europe Conference.
[3] Wei Tsang Ooi,et al. Workload characterization and cost-quality tradeoffs in MPEG-4 decoding on resource-constrained devices , 2005, 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005..
[4] G.E. Moore,et al. Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.
[5] Sharad Malik,et al. Power analysis of embedded software: a first step towards software power minimization , 1994, IEEE Trans. Very Large Scale Integr. Syst..
[6] H. T. Nagle,et al. A comparison of the noise sensitivity of nine QRS detection algorithms , 1990, IEEE Transactions on Biomedical Engineering.
[7] Fadi J. Kurdahi,et al. Fast area estimation to support compiler optimizations in FPGA-based reconfigurable systems , 2002, Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.
[8] Sharad Malik,et al. Guarded evaluation: pushing power management to logic synthesis/design , 1995, ISLPED '95.
[9] Glenn Leary,et al. Design of NoC for SoC with Multiple Use Cases Requiring Guaranteed Performance , 2010, 2010 23rd International Conference on VLSI Design.
[10] Paul Feautrier,et al. A New Solution to Coherence Problems in Multicache Systems , 1978, IEEE Transactions on Computers.
[11] Alan Jay Smith,et al. Reducing processor power consumption by improving processor time management in a single-user operating system , 1996, MobiCom '96.
[12] Hal Wasserman,et al. Comparing algorithm for dynamic speed-setting of a low-power CPU , 1995, MobiCom '95.
[13] Srinivasan Murali,et al. SUNMAP: a tool for automatic topology selection and generation for NoCs , 2004, Proceedings. 41st Design Automation Conference, 2004..
[14] Ho-Young Kim,et al. Top-Down Retargetable Fraemwork with Token-Level Design for Accelerating Simulation Speed of Processor Architecture , 2003 .
[15] S. W. Depp,et al. Technology directions for portable computers , 1995, Proc. IEEE.
[16] Tsutomu Yoshinaga,et al. High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core , 2006, The Journal of Supercomputing.
[17] Mary Jane Irwin,et al. Techniques for low energy software , 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.
[18] Radu Marculescu,et al. On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches , 2007, TODE.
[19] Andrew A. Chien,et al. Planar-adaptive routing: low-cost adaptive networks for multiprocessors , 1992, ISCA '92.
[20] Ming Li,et al. DyXY - a proximity congestion-aware deadlock-free dynamic routing method for network on chip , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[21] Hamid Sarbazi-Azad,et al. Multicast-Aware Mapping Algorithm for On-chip Networks , 2011, 2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing.
[22] Kai Li,et al. Storage alternatives for mobile computers , 1994, OSDI '94.
[23] Liam Goudge,et al. Thumb: reducing the cost of 32-bit RISC performance in portable and consumer applications , 1996, COMPCON '96. Technologies for the Information Superhighway Digest of Papers.
[24] Tsutomu Yoshinaga,et al. Parallel Queue Processor Architecture Based on Produced Order Computation Model , 2005, The Journal of Supercomputing.
[25] DANIEL MATTSSON,et al. Evaluation of synthesizable CPU cores , 2004 .
[26] R. K. Ursem. Multi-objective Optimization using Evolutionary Algorithms , 2009 .
[27] Arquimedes Canedo,et al. A new code generation algorithm for 2-offset producer order queue computation model , 2008, Comput. Lang. Syst. Struct..
[28] D. Bonn,et al. Two heads are better than one , 1999, Nature Methods.
[29] Patrick Schaumont,et al. Standards for system-level design: practical reality or solution in search of a question? , 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537).
[30] Akram Ben Ahmed,et al. Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC , 2010, 2010 International Conference on Broadband, Wireless Computing, Communication and Applications.
[31] Lionel M. Ni,et al. The Turn Model for Adaptive Routing , 1992, [1992] Proceedings the 19th Annual International Symposium on Computer Architecture.
[32] Javier Zalamea,et al. Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures , 2004, International Journal of Parallel Programming.
[33] Farid N. Najm,et al. A survey of power estimation techniques in VLSI circuits , 1994, IEEE Trans. Very Large Scale Integr. Syst..
[34] Tsutomu Yoshinaga,et al. Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core , 2005, EUC.
[35] Partha Pratim Pande,et al. Performance Evaluation for Three-Dimensional Networks-On-Chip , 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).
[36] Donald B. Alpert,et al. Architecture of the Pentium microprocessor , 1993, IEEE Micro.
[37] Thomas L. Martin,et al. Balancing batteries, power, and performance: system issues in cpu speed-setting for mobile computing , 1999 .
[38] Niraj K. Jha,et al. Express virtual channels: towards the ideal interconnection fabric , 2007, ISCA '07.
[39] Russell Tessier,et al. An architecture and compiler for scalable on-chip communication , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[40] Einar J. Aas,et al. An implementation of an embedded microprocessor core with support for executing byte compiled Java code , 2001, Proceedings Euromicro Symposium on Digital Systems Design.
[41] Frank Vahid,et al. A study of the speedups and competitiveness of FPGA soft processor cores using dynamic hardware/software partitioning , 2005, Design, Automation and Test in Europe.
[42] Manfred Glesner,et al. Multicast Parallel Pipeline Router Architecture for Network-on-Chip , 2008, 2008 Design, Automation and Test in Europe.
[43] P. Krishnan,et al. Thwarting the Power-Hungry Disk , 1994, USENIX Winter.
[44] Fernando Moraes,et al. Evaluation of Routing Algorithms on Mesh Based NoCs , 2004 .
[45] William J. Dally,et al. Express Cubes: Improving the Performance of k-Ary n-Cube Interconnection Networks , 1989, IEEE Trans. Computers.
[46] Vivek De,et al. A new technique for standby leakage reduction in high-performance circuits , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).
[47] Michael Wolfe,et al. High performance compilers for parallel computing , 1995 .
[48] J. Llosa,et al. Using Queues for Register File Organization in VLIW Architectures by Marcio , 1997 .
[49] James J. Kistler. Disconnected Operation in a Distributed File System , 1995, Lecture Notes in Computer Science.
[50] An-Yeu Wu,et al. Traffic- and Thermal-Aware Run-Time Thermal Management Scheme for 3D NoC Systems , 2010, 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip.
[51] Larry L. Biro,et al. Power considerations in the design of the Alpha 21264 microprocessor , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[52] Xiang Ling,et al. The design and implementation of arbiters for Network-on-chips , 2010, 2010 2nd International Conference on Industrial and Information Systems.
[53] Shekhar Y. Borkar,et al. Design challenges of technology scaling , 1999, IEEE Micro.
[54] Mahmut T. Kandemir,et al. Design and Management of 3D Chip Multiprocessors Using Network-in-Memory , 2006, 33rd International Symposium on Computer Architecture (ISCA'06).
[55] N. Bambos,et al. Mobile power management for maximum battery life in wireless communication networks , 1996, Proceedings of IEEE INFOCOM '96. Conference on Computer Communications.
[56] Barry B. Brey. The Intel Microprocessors , 2008 .
[57] Arquimedes Canedo,et al. A GCC-based Compiler for the Queue Register Processor (QRP-GCC) , 2006 .
[58] Luca P. Carloni,et al. Networks-on-chip in emerging interconnect paradigms: Advantages and challenges , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.
[59] R. Orglmeister,et al. The principles of software QRS detection , 2002, IEEE Engineering in Medicine and Biology Magazine.
[60] Edwin Hsing-Mean Sha,et al. Hardware/Software co-design with the HMS framework , 1996, J. VLSI Signal Process..
[61] Hiroki Matsutani,et al. Balanced Dimension-Order Routing for k-ary n-cubes , 2009, 2009 International Conference on Parallel Processing Workshops.
[62] Paul Horton,et al. A Quantitative Analysis of Disk Drive Power Management in Portable Computers , 1994, USENIX Winter.
[63] James E. Smith,et al. The microarchitecture of superscalar processors , 1995, Proc. IEEE.
[64] Alf Johansson,et al. On Connecting Cores to Packet Switched On-Chip Networks: A Case Study with MicroBlaze Processor Cores , 2004 .
[65] Scott Shenker,et al. Scheduling for reduced CPU energy , 1994, OSDI '94.
[66] Abderazek Ben Abdallah,et al. Design and Evaluation of a Complexity Effective Network-on-Chip Architecture on FPGA , 2009 .
[67] Edward S. Davidson,et al. Evaluating the Use of Register Queues in Software Pipelined Loops , 2001, IEEE Trans. Computers.
[68] David A. Koufaty,et al. Hyperthreading Technology in the Netburst Microarchitecture , 2003, IEEE Micro.
[69] Jürgen Becker,et al. Runtime adaptive multi-processor system-on-chip: RAMPSoC , 2008, 2008 IEEE International Symposium on Parallel and Distributed Processing.
[70] Dean M. Tullsen,et al. Interconnections in multi-core architectures: understanding mechanisms, overheads and scaling , 2005, 32nd International Symposium on Computer Architecture (ISCA'05).
[71] Bill Lin,et al. Design of application-specific 3D Networks-on-Chip architectures , 2008, 2008 IEEE International Conference on Computer Design.
[72] Giovanni De Micheli,et al. Readings in hardware / software co-design , 2001 .
[73] Giovanni De Micheli,et al. A complete network-on-chip emulation framework , 2005, Design, Automation and Test in Europe.
[74] Monica S. Lam,et al. RETROSPECTIVE : Software Pipelining : An Effective Scheduling Technique for VLIW Machines , 1998 .
[75] Jason Merrill. Generic and gimple: A new tree represen-tation for entire functions , 2003 .
[76] Trevor Mudge,et al. MiBench: A free, commercially representative embedded benchmark suite , 2001 .
[77] Nisha Checka,et al. Technology, performance, and computer-aided design of three-dimensional integrated circuits , 2004, ISPD '04.
[78] Akram Ben Ahmed,et al. ONoC-SPL: Customized Network-on-Chip (NoC) architecture and prototyping for data-intensive computation applications , 2012, 4th International Conference on Awareness Science and Technology.
[79] Massoud Pedram,et al. Power minimization in IC design: principles and applications , 1996, TODE.
[80] William J. Dally,et al. Flattened Butterfly Topology for On-Chip Networks , 2007, IEEE Comput. Archit. Lett..
[81] Luca Benini,et al. Analyzing on-chip communication in a MPSoC environment , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[82] Chita R. Das,et al. A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks , 2006, 33rd International Symposium on Computer Architecture (ISCA'06).
[83] Kevin D. Kissell. MIPS16: High-density MIPS for the Embedded Market1 , 1997 .
[84] Diego Novillo. Design and Implementation of Tree SSA , 2004 .
[85] Miodrag Potkonjak,et al. MediaBench: a tool for evaluating and synthesizing multimedia and communications systems , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.
[86] Krishnan Srinivasan,et al. Linear programming based techniques for synthesis of network-on-chip architectures , 2006, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..
[87] Mache Creeger,et al. Multicore CPUs for the Masses , 2005, QUEUE.
[88] Sujit Dey,et al. Efficient exploration of the SoC communication architecture design space , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).
[89] Robin Kravets,et al. Application‐driven power management for mobile communication , 2000, Wirel. Networks.
[90] Josep Llosa,et al. Quantitative Evaluation of Register Pressure on Software Pipelined Loops , 1998, International Journal of Parallel Programming.
[91] Fernando Gehm Moraes,et al. HERMES: an infrastructure for low area overhead packet-switching networks on chip , 2004, Integr..
[92] Rasmus Grøndahl Olsen. OCP based adapter for network-on-chip , 2005 .
[93] Brian T. Gold. BALANCING PERFORMANCE, AREA, AND POWER IN AN ON-CHIP NETWORK , 2003 .
[94] Ran Ginosar,et al. QNoC: QoS architecture and design process for network on chip , 2004, J. Syst. Archit..
[95] Susumu Horiguchi,et al. High performance hierarchical torus network under matrix transpose traffic patterns , 2004, 7th International Symposium on Parallel Architectures, Algorithms and Networks, 2004. Proceedings..
[96] David W. Wall,et al. Limits of instruction-level parallelism , 1991, ASPLOS IV.
[97] Kees Goossens,et al. AEthereal network on chip: concepts, architectures, and implementations , 2005, IEEE Design & Test of Computers.
[98] Niraj K. Jha,et al. COSYN: Hardware-software co-synthesis of heterogeneous distributed embedded systems , 1999, IEEE Trans. Very Large Scale Integr. Syst..
[99] Mary G Carey,et al. Electrocardiographic Predictors of Sudden Cardiac Death , 2008, The Journal of cardiovascular nursing.
[100] Jason D. Lee,et al. NoCBench : A Benchmarking Platform for Network on Chip , 2009 .
[101] Krishna M. Sivalingam,et al. Design and analysis of low‐power access protocols for wireless and mobile ATM networks , 2000, Wirel. Networks.
[102] Abderazek Ben Abdallah. Dynamic instruction issue algorithm and a queue execution model toward the design of hybrid processor architecture , 2002 .
[103] Scott Mahlke,et al. Scalar program performance on multiple-instruction-issue processors with a limited number of registers , 1992, Proceedings of the Twenty-Fifth Hawaii International Conference on System Sciences.
[104] Axel Jantsch,et al. A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.
[105] Jacob R. Lorch,et al. A complete picture of the energy consumption of a portable computer , 1995 .
[106] Wolfgang Rosenstiel,et al. Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures , 2007, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007).
[107] Luca Benini,et al. System-level power optimization: techniques and tools , 1999, ISLPED '99.
[108] Masahiro Sowa,et al. Basic Network-on-Chip Interconnection for Future Gigascale MCSoCs Applications: Communication and Computation Orthogonalization , 2006 .
[109] Masahiro Sowa,et al. Design and architecture for an embedded 32-bit QueueCore , 2006, J. Embed. Comput..
[110] Fabian Wolf. Behavioral Intervals in Embedded Software: Timing and Power Analysis of Embedded Real-Time Software Processes , 2002 .
[111] Henry Hoffmann,et al. On-Chip Interconnection Architecture of the Tile Processor , 2007, IEEE Micro.
[112] Hideo Maejima,et al. Design and Architecture for Low-power/High-Speed RISC Microprocessor: SuperH , 1997 .
[113] Oliver Chiu-sing Choy,et al. A low-latency NoC router with lookahead bypass , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.
[114] Gürhan Küçük,et al. Energy Efficient Register Renaming , 2003, PATMOS.
[115] Mike O'Connor,et al. PicoJava: A Direct Execution Engine For Java Bytecode , 1998, Computer.
[116] David A. Patterson,et al. Computer Architecture - A Quantitative Approach (4. ed.) , 2007 .
[117] Vivek Tiwari,et al. Reducing power in high-performance microprocessors , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[118] Pradeep K. Dubey,et al. How Multimedia Workloads Will Change Processor Design , 1997, Computer.
[119] Anant Agarwal,et al. Directory-based cache coherence in large-scale multiprocessors , 1990, Computer.
[120] Peter Ramm,et al. Handbook of 3D integration : technology and applications of 3D integrated circuits , 2012 .
[121] H. Takahashi. A 100 MIPS High Speed and Low Power Digital Signal Processor , 1997 .
[122] Alan Jay Smith,et al. Software strategies for portable computer energy management , 1998, IEEE Wirel. Commun..
[123] Andrew D. Booth,et al. A SIGNED BINARY MULTIPLICATION TECHNIQUE , 1951 .
[124] Greg Welch,et al. A survey of power management techniques in mobile computing operating systems , 1995, OPSR.
[125] Jörg Henkel,et al. Hardware-software cosynthesis for microcontrollers , 1993, IEEE Design & Test of Computers.
[126] W. Dally,et al. Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[127] Masahiro Sowa,et al. Design of a superscalar processor based on queue machine computation model , 1999, 1999 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM 1999). Conference Proceedings (Cat. No.99CH36368).
[128] Vincenzo Catania,et al. A methodology for design of application specific deadlock-free routing algorithms for NoC systems , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).
[129] Ben A. Abderazek,et al. An Efficient Algorithm and Embedded Multicore Implementation of ECG Analysis in Multi-lead Electrocardiogram Records , 2010, 2010 39th International Conference on Parallel Processing Workshops.
[130] Simon W. Moore,et al. Low-latency virtual-channel routers for on-chip networks , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..
[131] Benjamin Bishop,et al. The design of a register renaming unit , 1999, Proceedings Ninth Great Lakes Symposium on VLSI.