Integration challenges for multi-gate devices

The FinFET transistor is the most widely studied and known multi-gate architecture that has the potential to be scaled to beyond the 45 nm technology node. In this paper a number of integration issues have been addressed. In first section the patterning challenges have been discussed. Due to the particular layout of the FinFET devices a variation in fin width is seen due to the rounding of the fin opening. This problem can be addressed by looking at alternative litho settings and OPC. Next to that topography plays an important in patterning the gate. It is seen that the optimization of the different OE times is key in achieving a controlled gate profile without poly residues. Techniques like poly etch-back can be used to alleviate the topography issues as much as possible. Threshold voltage tuning with implantation is extremely difficult for narrow fin devices. Workfunction tuning by either deposited metal gate or full silicidation is seen as a more viable solution. The extensions and deep source/drain areas need to be as conformal as possible in order to avoid the dominance of the top channel over the sidewalls. However, conventional implantation techniques are unsuitable and alternative implantation techniques need to be investigated. Next to that, when high density is needed, the fin spacing will limit the allowed tilt angle due to implant shadowing. The sidewall crystal orientation is different from that of the top channel and this will impact the mobility of holes and electrons in a different way. Rotation of the fins over 45 degrees, the use of strained layers and strained SiGe source/drain have been briefly discussed as possible solutions to tackle this problem. Finally, the impact of the fin width on R/sub SD/ has been shown. Elevated source/drain has been brought forward as a solution to this problem.

[1]  Vincent Wiaux,et al.  Challenges in patterning 45nm node multiple-gate devices and SRAM cells , 2004 .

[2]  Rita Rooyackers,et al.  The etchback approach: Enlarged process window for MuGFET gate etching , 2006 .

[3]  R. Rooyackers,et al.  A functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm fin widths applicable for the 45-nm CMOS node , 2004, IEEE Electron Device Letters.

[4]  C. Hu,et al.  FinFET-a self-aligned double-gate MOSFET scalable to 20 nm , 2000 .

[5]  M. Vinet,et al.  Experimental gate misalignment analysis on double gate SOI MOSFETs , 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

[6]  R. Rooyackers,et al.  A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[7]  R. Rooyackers,et al.  25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si/sub 0.8/Ge/sub 0.2/ in the source and drain regions , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[8]  R. Rooyackers,et al.  CMP-less integration of fully Ni-silicided metal gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[9]  Rita Rooyackers,et al.  NMOS and PMOS triple gate devices with mid-gap metal gate on oxynitride and Hf based gate dielectrics , 2005 .

[10]  Ying Zhang,et al.  Extension and source/drain design for high-performance FinFET devices , 2003 .

[11]  U. Langmann,et al.  Short-channel vertical sidewall MOSFETs , 2001 .

[12]  D. Delille,et al.  Highly performant double gate MOSFET realized with SON process , 2003, IEEE International Electron Devices Meeting 2003.

[13]  J. Kavalieros,et al.  High performance fully-depleted tri-gate CMOS transistors , 2003, IEEE Electron Device Letters.

[14]  N. Collaert,et al.  Layout density analysis of FinFETs , 2003, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003..

[15]  Kok Wai Wong,et al.  Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation , 2002, Digest. International Electron Devices Meeting,.

[16]  M. Ieong,et al.  Threshold voltage control in NiSi-gated MOSFETs through silicidation induced impurity segregation (SIIS) , 2003, IEEE International Electron Devices Meeting 2003.

[17]  Jong-Tea Park,et al.  Pi-Gate SOI MOSFET , 2001, IEEE Electron Device Letters.

[18]  Y. Yeo,et al.  25 nm CMOS Omega FETs , 2002, Digest. International Electron Devices Meeting,.

[19]  Chenming Hu,et al.  Nanoscale CMOS spacer FinFET for the terabit era , 2002, IEEE Electron Device Letters.

[20]  T. Skotnicki,et al.  Totally silicided (CoSi/sub 2/) polysilicon: a novel approach to very low-resistive gate (/spl sim/2/spl Omega///spl square/) without metal CMP nor etching , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).