Proteo: The Development of a Practical Network-on-Chip

This thesis discusses Network-on-Chip communications in digital systems. The subject matter is introduced at length, with a summary of the main arguments in favour of the adoption of networked Systems-on-Chip, and an overview of configurations proposed in the literature. The author’s own Proteo Network-on-Chip is then presented. Proteo tries to fulfill most future Network-on-Chip requirements while avoiding major overheads. A discussion of many of the trade-offs in network design is included, as well as the reasoning for specific architectural decisions. Proteo compares favourably to most Networks-on-Chip in terms of simplicity and economy. Special stress is put on the definition of a design methodology and the development of software tools to complement Proteo. The description of Proteo is illustrated with examples taken from an ongoing project consisting in the practical implementation of a multimedia processing platform. The topic of Network-on-Chip is wide-ranging and, although the basic groundwork is in place, a lot of work is still missing. In the last chapter of this thesis, a summary of Proteo achievements and planned futute developments is included.

[1]  J. Sansom W. S. W. , 1851 .

[2]  Jari Nurmi,et al.  Issues in the development of a practical NoC: the Proteo concept , 2004, Integr..

[3]  Alain Greiner,et al.  A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.

[4]  Tapani Ahonen,et al.  Topology optimization for application-specific networks-on-chip , 2004, SLIP '04.

[5]  Altamiro Amadeu Susin,et al.  SoCIN: a parametric and scalable network-on-chip , 2003, 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings..

[6]  M. Birnbaum,et al.  How VSIA Answers the SOC Dilemma , 1999, Computer.

[7]  George Varghese,et al.  Efficient fair queueing using deficit round robin , 1995, SIGCOMM '95.

[8]  Jari Nurmi,et al.  From Buses to Networks , 2005 .

[9]  Jari Nurmi,et al.  Topology design for global link optimization in application specific network-on-chips , 2004, 2004 International Symposium on System-on-Chip, 2004. Proceedings..

[10]  Andrew Lines,et al.  Asynchronous interconnect for synchronous SoC design , 2004, IEEE Micro.

[11]  Benjamin Melamed,et al.  Hybrid discrete-continuous fluid-flow simulation , 2001, SPIE ITCom.

[12]  Jari Nurmi,et al.  Proteo: A New Approach t o Network-on-Chip , 2002 .

[13]  Wojciech Maly,et al.  Design for manufacturability in submicron domain , 1996, Proceedings of International Conference on Computer Aided Design.

[14]  Martin Peschke,et al.  Design and Validation of Computer Protocols , 2003 .

[15]  Wolfgang Fichtner,et al.  Globally-asynchronous locally-synchronous architectures to simplify the design of on-chip systems , 1999, Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454).

[16]  Antonio Rubio,et al.  Noise generation and coupling mechanisms in deep-submicron ICs , 2002, IEEE Design & Test of Computers.

[17]  Jari Nurmi,et al.  An IP-Based On-Chip Packet-Switched Network , 2003, Networks on Chip.

[18]  Ahmed Amine Jerraya,et al.  Mixed-level cosimulation for fine gradual refinement of communication in SoC design , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[19]  Michael Stumm,et al.  Hector: a hierarchically structured shared-memory multiprocessor , 1991, Computer.

[20]  Mikko Alho Implementation of flexible network nodes in PROTEO network , 2002 .

[21]  James P. Braselton,et al.  CHAPTER 9 , 2019, On Job, Volume 1.

[22]  J. Nurmi,et al.  Reusable XGFT interconnect IP for network-on-chip implementations , 2004, 2004 International Symposium on System-on-Chip, 2004. Proceedings..

[23]  H. Zimmermann,et al.  OSI Reference Model - The ISO Model of Architecture for Open Systems Interconnection , 1980, IEEE Transactions on Communications.

[24]  Stephen B. Furber,et al.  Chain: A Delay-Insensitive Chip Area Interconnect , 2002, IEEE Micro.

[25]  Jari Nurmi,et al.  Integration of a NOC-based multimedia processing platform , 2005, International Conference on Field Programmable Logic and Applications, 2005..

[26]  J. A. Rowson,et al.  Blocking in a system on a chip , 1996 .

[27]  Russell Tessier,et al.  ASOC: a scalable, single-chip communications architecture , 2000, Proceedings 2000 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00622).

[28]  Jari Nurmi,et al.  Block-wise extraction of Rent's exponents for an extensible processor , 2003, IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings..

[29]  Lars Liebmann,et al.  CAD computation for manufacturability: can we save VLSI technology from itself? , 2002, ICCAD 2002.

[30]  Johnny Öberg,et al.  Lowering power consumption in clock by using globally asynchronous locally synchronous design style , 1999, DAC '99.

[31]  Jari Nurmi,et al.  IMPLEMENTATION OF INTERFACE ROUTER IP FOR PROTEO NETWORK-ON-CHIP , 2003 .

[32]  Stephen B. Furber The return of asynchronous logic , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[33]  Alberto L. Sangiovanni-Vincentelli,et al.  Constraint-driven communication synthesis , 2002, DAC '02.

[34]  Kurt Keutzer,et al.  A global wiring paradigm for deep submicron design , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[35]  William J. Dally,et al.  Performance Analysis of k-Ary n-Cube Interconnection Networks , 1987, IEEE Trans. Computers.

[36]  Peter Alan Lee,et al.  Fault Tolerance , 1990, Dependable Computing and Fault-Tolerant Systems.

[37]  C. D. Gelatt,et al.  Optimization by Simulated Annealing , 1983, Science.

[38]  Alberto L. Sangiovanni-Vincentelli,et al.  Addressing the system-on-a-chip interconnect woes through communication-based design , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[39]  Raj Jain,et al.  UBR+: improving performance of TCP over ATM-UBR service , 1997, Proceedings of ICC'97 - International Conference on Communications.

[40]  Mario Gerla,et al.  On the Topological Design of Distributed Computer Networks , 1977, IEEE Trans. Commun..

[41]  Kurt Keutzer,et al.  Getting to the bottom of deep submicron , 1998, ICCAD '98.

[42]  George Varghese,et al.  Efficient fair queueing using deficit round-robin , 1996, TNET.

[43]  Alberto L. Sangiovanni-Vincentelli,et al.  System-level design: orthogonalization of concerns andplatform-based design , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[44]  Jari Nurmi,et al.  Interconnect IP node for future system-on-chip designs , 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002.

[45]  Thomas A. Henzinger,et al.  INTERFACE-BASED DESIGN , 2005 .

[46]  Steve Furber Breaking step: the return of asynchronous logic , 1993 .

[47]  Shashi Kumar,et al.  On Packet Switched Networks for On-Chip Communication , 2003, Networks on Chip.

[48]  Sujit Dey,et al.  An Interconnect Architecture for Networking Systems on Chips , 2002, IEEE Micro.

[49]  Luca Benini,et al.  A novel approach for network on chip emulation , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[50]  Himanshu Kaul,et al.  Future performance challenges in nanometer design , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[51]  Xin Wang,et al.  Asynchronous network node design for network-on-chip , 2005, International Symposium on Signals, Circuits and Systems, 2005. ISSCS 2005..

[52]  Axel Jantsch,et al.  Networks on chip , 2003 .

[53]  Kees G. W. Goossens,et al.  Networks on silicon: combining best-effort and guaranteed services , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[54]  Axel Jantsch,et al.  A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[55]  Sharad Malik,et al.  A disciplined approach to the development of platform architectures , 2002 .

[56]  T. Hamalainen,et al.  Overview of bus-based system-on-chip interconnections , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[57]  David R. Stauffer,et al.  Core Design and System-on-a-Chip Integration , 1997, IEEE Des. Test Comput..

[58]  Stefan Rusu Clock Distribution for High Performance Designs , 2005 .

[59]  Axel Jantsch,et al.  The Nostrum backbone-a communication protocol stack for Networks on Chip , 2004, 17th International Conference on VLSI Design. Proceedings..

[60]  Luciano Lavagno,et al.  De-synchronization: asynchronous circuits from synchronous specifications , 2003, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..

[61]  Axel Jantsch,et al.  Network on Chip : An architecture for billion transistor era , 2000 .

[62]  Duncan J. Watts,et al.  Collective dynamics of ‘small-world’ networks , 1998, Nature.

[63]  Daniel C. Edelstein,et al.  On-chip wiring design challenges for gigahertz operation , 2001, Proc. IEEE.

[64]  David Blaauw,et al.  Impact of lithography variability on statistical timing behavior , 2004, SPIE Advanced Lithography.

[65]  Arunita Jaekel,et al.  A genetic algorithm for optimization of logical topologies in optical networks , 2002, Proceedings 16th International Parallel and Distributed Processing Symposium.

[66]  Baruch Awerbuch,et al.  Universal-stability results and performance bounds for greedy contention-resolution protocols , 2001, JACM.

[67]  Richard B. Fair,et al.  Challenges to manufacturing submicron, ultra-large scale integrated circuits , 1990, Proc. IEEE.

[68]  Anup Kumar,et al.  Genetic algorithm based approach for designing computer network topology , 1993, CSC '93.

[69]  Jari Nurmi,et al.  VHDL-based simulation environment for Proteo NoC , 2002, Seventh IEEE International High-Level Design Validation and Test Workshop, 2002..

[70]  W. T. Coston Issues for fabless design companies moving towards deep submicron system on a chip design , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[71]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[72]  Andrew B. Kahng,et al.  Manufacturing-aware physical design , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

[73]  David B. Gustavson,et al.  Scalable Coherent Interface , 1990, COMPEURO'90: Proceedings of the 1990 IEEE International Conference on Computer Systems and Software Engineering@m_Systems Engineering Aspects of Complex Computerized Systems.

[74]  L. Benini,et al.  Xpipes: a network-on-chip architecture for gigascale systems-on-chip , 2004, IEEE Circuits and Systems Magazine.

[75]  R. Jan,et al.  Topological optimization of a communication network subject to a reliability constraint , 1993 .

[76]  Jason Cong,et al.  Interconnect design for deep submicron ICs , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[77]  Hanan Luss,et al.  Topological network design for SONET ring architecture , 1998, IEEE Trans. Syst. Man Cybern. Part A.

[78]  M. Coppola,et al.  Spidergon: a novel on-chip communication network , 2004, 2004 International Symposium on System-on-Chip, 2004. Proceedings..

[79]  Ran Ginosar,et al.  QNoC: QoS architecture and design process for network on chip , 2004, J. Syst. Archit..