论文信息 - Area-Time Optimal VLSI Integer Multiplier with Minimum Computation Time

Area-Time Optimal VLSI Integer Multiplier with Minimum Computation Time

According to VLSI theory, [logn, √n] is the range of computation times for which there may exist an AT2-optimal multiplier of n-bit integers. Such networks were previously known for the time range [Ω(log2n), 0(√n)]; in this paper we settle this theoretical question, by exhibiting a-class of AT2-optimal multipliers with computation times [Ω(logn), 0(n1/2)]. Our designs are based on the DFT on a Fermat ring, whose elements are represented in a redundant radix-4 form to ensure 0(1) addition time.

Kurt Mehlhorn | Franco P. Preparata

[1] C. Thomborson,et al. Area-time complexity for VLSI , 1979, STOC.

[2] Christopher S. Wallace,et al. A Suggestion for a Fast Multiplier , 1964, IEEE Trans. Electron. Comput..

[3] Franco P. Preparata,et al. The cube-connected-cycles: A versatile network for parallel computation , 1979, 20th Annual Symposium on Foundations of Computer Science (sfcs 1979).

[4] H. T. Kung,et al. The chip complexity of binary arithmetic , 1980, STOC '80.

[5] Alfred V. Aho,et al. The Design and Analysis of Computer Algorithms , 1974 .

[6] Jean Vuillemin,et al. A very fast multiplication algorithm for VLSI implementation , 1983, Integr..

[7] H. T. Kung,et al. The Area-Time Complexity of Binary Multiplication , 1981, JACM.

[8] Harold Abelson,et al. Information transfer and area-time tradeoffs for VLSI multiplication , 1980, CACM.

[9] Kurt Mehlhorn,et al. AT2-optimal VLSI integer division and integer square rooting , 1984, Integr..

[10] Anatolij A. Karatsuba,et al. Multiplication of Multidigit Numbers on Automata , 1963 .

[11] Franco P. Preparata,et al. Area-Time Optimal VLSI Networks for Computing Integer Multiplications and Discrete Fourier Transform , 1981, ICALP.