Power Profiling-Guided Floorplanner for Thermal Optimization in 3D Multiprocessor Architectures

3D integration has become one of the most promising techniques for the integration future multi-core processors, since it improves performance and reduces power consumption by decreasing global wire length. However, 3D integration causes serious thermal problems since the closer proximity of heat generating dies makes existing thermal hotspots more severe. Thermal-aware floorplanners can play an important role to improve the thermal profile, but they have failed in considering the dynamic power profiles of the applications. This paper proposes a novel thermal-aware floorplanner guided by the power profiling of a set of benchmarks that are representative of the application scope. The results show how our approach outperforms the thermal metrics as compared with the worst-case scenario usually considered in "traditional" thermal-aware floorplanners.

[1]  Gary B. Lamont,et al.  Evolutionary Algorithms for Solving Multi-Objective Problems , 2002, Genetic Algorithms and Evolutionary Computation.

[2]  Huazhong Yang,et al.  Accurate temperature-dependent integrated circuit leakage power estimation is easy , 2007 .

[3]  Sung Kyu Lim,et al.  Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Elaheh Bozorgzadeh,et al.  Statistical power profile correlation for realistic thermal estimation , 2008, 2008 Asia and South Pacific Design Automation Conference.

[5]  Sachin S. Sapatnekar,et al.  Partition-driven standard cell thermal placement , 2003, ISPD '03.

[6]  Xin Li,et al.  A novel thermal optimization flow using incremental floorplanning for 3D ICs , 2009, 2009 Asia and South Pacific Design Automation Conference.

[7]  Håkan Grahn,et al.  ParMiBench - An Open-Source Benchmark for Embedded Multiprocessor Systems , 2010, IEEE Computer Architecture Letters.

[8]  Rolf Drechsler,et al.  Applications of Evolutionary Computing, EvoWorkshops 2008: EvoCOMNET, EvoFIN, EvoHOT, EvoIASP, EvoMUSART, EvoNUM, EvoSTOC, and EvoTransLog, Naples, Italy, March 26-28, 2008. Proceedings , 2008, EvoWorkshops.

[9]  Hsien-Hsin S. Lee,et al.  Thermal-aware 3D Microarchitectural Floorplanning , 2004 .

[10]  Narayanan Vijaykrishnan,et al.  Thermal-aware floorplanning using genetic algorithms , 2005, Sixth international symposium on quality electronic design (isqed'05).

[11]  Shekhar Y. Borkar,et al.  Design challenges of technology scaling , 1999, IEEE Micro.

[12]  Xin Yao,et al.  A Memetic Algorithm for VLSI Floorplanning , 2007, IEEE Transactions on Systems, Man, and Cybernetics, Part B (Cybernetics).

[13]  Israel Koren,et al.  Simulated Annealing Based Temperature Aware Floorplanning , 2007, J. Low Power Electron..

[14]  Kevin Skadron,et al.  A Case for Thermal-Aware Floorplanning at the Microarchitectural Level , 2005, J. Instr. Level Parallelism.

[15]  Kalyanmoy Deb,et al.  A fast and elitist multiobjective genetic algorithm: NSGA-II , 2002, IEEE Trans. Evol. Comput..

[16]  Maolin Tang,et al.  A Slicing Structure Representation for the Multi-layer Floorplan Layout Problem , 2004, EvoWorkshops.

[17]  Martin D. F. Wong,et al.  A matrix synthesis approach to thermal placement , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  David Atienza,et al.  3D Thermal-aware floorplanner for many-core single-chip systems , 2011, 2011 12th Latin American Test Workshop (LATW).

[19]  Igor L. Markov,et al.  Fixed-outline floorplanning: enabling hierarchical design , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[20]  Yiming Li,et al.  Temperature Aware Floorplanning via Geometry Programming , 2008, CSE 2008.

[21]  Gary B. Lamont,et al.  Evolutionary Algorithms for Solving Multi-Objective Problems (Genetic and Evolutionary Computation) , 2006 .

[22]  Luca Benini,et al.  Exploring “temperature-aware” design in low-power MPSoCs , 2007, Proceedings of the Design Automation & Test in Europe Conference.

[23]  Jason Cong,et al.  A thermal-driven floorplanning algorithm for 3D ICs , 2004, ICCAD 2004.