A Comparison between Statecharts and State Transition Assertions

Abstract This paper compares statecharts, a specification formalism for reactive systems, to state transition assertions, a verification method for hard real-time systems. While these two methods are used for different tasks and they take different points of view in describing a system, it is useful to compare them to determine what is necessary in a formal specification notation for real-time systems. In this paper, we conclude with a list of issues that need to be resolved when integrating formal verification with a specification notation. The future goal of this work is to provide a more readable front-end specification formalism which can be used for verification. The purpose of doing a formal verification of specifications is to check for correctness early in the system development process and discover errors which can prove costly in later stages. If a more readable notation like statecharts is embedded in the theorem-prover, HOL (Higher Order Logic), it would provide the tools necessary to do mechanized verification.