Substrate Engineering for VTH-Scaling at Low Supply Voltage (1.5-3 V) in ULSIs

A substrate engineering method is proposed to scale down Vrn at low supply voltage(1.5-3V) without punchthrough. This guideline results from a netr interpretation of the relationship between Vrn and nininurn channel length LEFF at which punchthrough is controlled. The most pronising punchthrough stopper should be laid in the depth between 0.05 p n and the source-drain junction depth. It results not only in suppression of punchthrough but also reduction of body effect and junction capacitance without affecting Vrn excessively. As a result, LEFF below 0.3 pm and 0.2V Vtn can be achieved sinultaneously.