FPGA Design of Optimized CIC Interpolator for DSP based Wireless Communication Systems

In this paper an efficient multiplier less technique is presented to design and implement a high speed CIC interpolator for wireless applications like SDR and GSM. The implementation is based on efficient utilization of embedded LUTs of the target device to enhance the speed of proposed design. It is an efficient method used to design and implement CIC interpolator because the use of embedded LUTs not only increases the speed but also saves the resources on the target device. The fully pipelined CIC interpolator has been designed with Matlab, simulated with Modelsim, synthesized with Xilinx Synthesis Tool (XST), and implemented on Spartan-3E based XC3s500e- 4fg320 target device. The proposed design can be operated at an estimated frequency of 166.5 MHz by consuming very less resources available on target device to provide cost effective solution for wireless communication systems. The power consumption of the proposed design has been 0.08098W at 27.1 degree C junction temperature.