A 3D physical design flow based on Open Access

3D IC technologies have recently attracted great attention due to the potential performance improvement, power consumption reduction and heterogeneous integration. In this paper we present a 3D physical design flow based on OpenAccess (named 3D-Craft) to facilitate the rapid adoption of 3D technology. The OpenAccess extension for 3D-Craft is discussed, and the key components including the 3D placer mPL-3D and the 3D router TMARS are presented. We also demonstrate the application of 3D-Craft for the 3D physical design of an open-source processor, and show that the 3D implementation can reduce both the half-perimeter wirelength and the routed wirelength by about 30% compared to the 2D implementation.

[1]  Jian Xu,et al.  Demystifying 3D ICs: the pros and cons of going vertical , 2005, IEEE Design & Test of Computers.

[2]  Sachin S. Sapatnekar,et al.  Placement of 3D ICs with Thermal and Interlayer Via Considerations , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[3]  Sachin S. Sapatnekar,et al.  Temperature-aware routing in 3D ICs , 2006, Asia and South Pacific Conference on Design Automation, 2006..

[4]  Yici Cai,et al.  Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  Yao-Wen Chang,et al.  TCG: a transitive closure graph-based representation for non-slicing floorplans , 2001, DAC '01.

[6]  Jason Cong,et al.  Thermal via planning for 3-D ICs , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[7]  Sachin Sapatnekar,et al.  Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach , 2003, ICCAD 2003.

[8]  Martin D. F. Wong,et al.  Floorplanning for 3-D VLSI design , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[9]  Qiang Zhou,et al.  Thermal aware placement in 3D ICs using quadratic uniformity modeling approach , 2009, Integr..

[10]  Sheqin Dong,et al.  3D CBL: An Efficient Algorithm for General 3-Dimensional Packing Problems * , 2005 .

[11]  Jason Cong,et al.  A Robust Mixed-Size Legalization and Detailed Placement Algorithm , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  Hai Zhou,et al.  3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits , 2007, ICCAD 2007.

[13]  Jason Cong,et al.  Thermal-Aware 3D IC Placement Via Transformation , 2007, 2007 Asia and South Pacific Design Automation Conference.

[14]  Yoji Kajitani,et al.  How does partitioning matter for 3D floorplanning? , 2006, GLSVLSI '06.

[15]  Yan Zhang,et al.  Thermal-driven multilevel routing for 3D ICs , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[16]  M. Turowski,et al.  Fast, automated thermal simulation of three-dimensional integrated circuits , 2004, The Ninth Intersociety Conference on Thermal and Thermomechanical Phenomena In Electronic Systems (IEEE Cat. No.04CH37543).

[17]  Jason Cong,et al.  A multilevel analytical placement for 3D ICs , 2009, 2009 Asia and South Pacific Design Automation Conference.

[18]  Li Shang,et al.  3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[19]  Shamik Das,et al.  Design automation and analysis of three-dimensional integrated circuits , 2004 .

[20]  A. S. Grove.  Physics and Technology of Semiconductor Devices , 1967 .

[21]  Jason Cong,et al.  A thermal-driven floorplanning algorithm for 3D ICs , 2004, ICCAD 2004.