Hardware Implementation of a Real Time Image Compression

Real time processing of image deals with applying all required operations within a range of time not exceed the acceptable time of human eyes. Real time processing does not realized on standalone computer, so it need special hardware. The big challenge of image processing work is the processing time, in which there are big amount of data (pixels) that must be processed at a specific time. The most important objective aspect of this work and any image processing algorithm (software or hardware) is how to implement it in an efficient way via the effective management of the scheduling of the processing jobs and time allocated for each job. This work try to avoid this problem by inserting a Raspberry Pi device which is working as microcomputer and has the ability to work with image, video, audio and data. Compensating between hardware and software is very important to achieve an efficient implemented system. This work mixing between hardware (Raspberry Pi device) and the software compression algorithm to reach acceptable low cost and high speed operated system. The synchronization between hardware and software leads to an efficient architecture that can achieve the real time processing.

[1]  Rebecca Bruce,et al.  Changing the world with a Raspberry Pi , 2013 .

[2]  Andreas Uhl,et al.  Parallel JPEG2000 image coding on multiprocessors , 2002, Proceedings 16th International Parallel and Distributed Processing Symposium.

[3]  L. Nozal,et al.  A new vision system: programmable logic devices and digital signal processor architecture (PLD+DSP) , 1991, Proceedings IECON '91: 1991 International Conference on Industrial Electronics, Control and Instrumentation.

[4]  R. Lavanya,et al.  High Speed, Low complexity, Folded, Polymorphic Wavelet Architecture using Reconfigurable Hardware , 2010 .

[5]  Guido Masera,et al.  Multiplierless, Folded 9/7– 5/3 Wavelet VLSI Architecture , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[6]  Hemantkumar H. Nikhare,et al.  A Detailed Review on Architectures for 2-DWT by using Radix-4 Booth Multiplier , 2015 .

[7]  K.G. Oweiss,et al.  A systems approach for data compression and latency reduction in cortically controlled brain machine interfaces , 2006, IEEE Transactions on Biomedical Engineering.

[8]  Gareth Halfacree,et al.  Raspberry Pi User Guide , 2012 .

[9]  I. Daubechies Orthonormal bases of compactly supported wavelets , 1988 .

[10]  Richard Heeks,et al.  Ultra-low-cost computing and developing countries , 2013, CACM.

[11]  Michael W. Marcellin,et al.  An overview of JPEG-2000 , 2000, Proceedings DCC 2000. Data Compression Conference.

[12]  Liang-Gee Chen,et al.  Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[13]  S. Mallat A wavelet tour of signal processing , 1998 .

[14]  M. Suresh Babu,et al.  Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Packet Transform , 2010 .

[15]  Sven Helmer,et al.  Affordable and Energy-Efficient Cloud Computing Clusters: The Bolzano Raspberry Pi Cloud Cluster Experiment , 2013, 2013 IEEE 5th International Conference on Cloud Computing Technology and Science.

[16]  Liang-Gee Chen,et al.  Generic RAM-based architecture for two-dimensional discrete wavelet transform with line-based method , 2002, Asia-Pacific Conference on Circuits and Systems.

[17]  Chaitali Chakrabarti,et al.  A VLSI architecture for lifting-based forward and inverse wavelet transform , 2002, IEEE Trans. Signal Process..

[18]  S. Srinivasan,et al.  VLSI implementation of 2-D DWT/IDWT cores using 9/7-tap filter banks based on the non-expansive symmetric extension scheme , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[19]  Stéphane Mallat,et al.  A Theory for Multiresolution Signal Decomposition: The Wavelet Representation , 1989, IEEE Trans. Pattern Anal. Mach. Intell..

[20]  V. K. Bairagi,et al.  Hardware Design of 2-D High Speed DWT by using Multiplierless 5/3 Wavelet Filters , 2012 .

[21]  A. Vijayalakshmi,et al.  Design and Implementation of 3-D DWT for Video Processing Applications , 2013 .

[22]  Michel Barlaud,et al.  Image coding using wavelet transform , 1992, IEEE Trans. Image Process..

[23]  Joseph Zambreno,et al.  A Reconfigurable Architecture for Secure Multimedia Delivery , 2010, 2010 23rd International Conference on VLSI Design.

[24]  Jie Guo,et al.  Efficient FPGA implementation of modified DWT for JPEG2000 , 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

[25]  Guido Masera,et al.  Low-Complexity, Efficient 9/7 Wavelet Filters VLSI Implementation , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[26]  Yau-Hwang Kuo,et al.  VLSI design af a DWT/modified efficient SPIHT based image codec , 2003, Fourth International Conference on Information, Communications and Signal Processing, 2003 and the Fourth Pacific Rim Conference on Multimedia. Proceedings of the 2003 Joint.

[27]  Surya S. Durbha,et al.  Feature Identification via a Combined ICA–Wavelet Method for Image Information Mining , 2010, IEEE Geoscience and Remote Sensing Letters.

[28]  M. Jeyaprakash FPGA Implementation of Discrete Wavelet Transform (DWT) for JPEG 2000 , 2009 .

[29]  Joan Carletta,et al.  A comparison of hardware implementations of the biorthogonal 9/7 DWT: convolution versus lifting , 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.

[30]  Mohan Vishwanath The recursive pyramid algorithm for the discrete wavelet transform , 1994, IEEE Trans. Signal Process..

[31]  Woon-Seng Gan,et al.  Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Packet Transform , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[32]  G. A Theory for Multiresolution Signal Decomposition : The Wavelet Representation , 2004 .

[33]  Santiago Lorenzo,et al.  Real time and low cost image processing architecture based on programmable logic devices (PLD) , 1991, Proceedings IROS '91:IEEE/RSJ International Workshop on Intelligent Robots and Systems '91.

[34]  A Karthikeyan,et al.  An Efficient VLSI Architecture for 3D DWT Using Lifting Scheme , 2012 .

[35]  Lin Wu,et al.  Efficient Multi-Input/Multi-Output VLSI Architecture for Two-Dimensional Lifting-Based Discrete Wavelet Transform , 2011, IEEE Transactions on Computers.

[36]  I. Daubechies,et al.  Biorthogonal bases of compactly supported wavelets , 1992 .

[37]  Keshab K. Parhi,et al.  High-Speed VLSI Implementation of 2-D Discrete Wavelet Transform , 2008, IEEE Transactions on Signal Processing.

[38]  E. Casseau,et al.  Based Design 2000 Session 3 B : IP / Core / SoC Design High Level Design and Synthesis of a Discrete Wavelet Transform Virtual Component for Image Compression , 2022 .