Clock duty-ratio correcting circuit capable of reducing overshooting and jittering

The utility model relates to a clock duty-ratio correcting circuit capable of reducing overshooting and jittering. The correcting circuit comprises a first DCC (duty-cycle corrector) delay chain, a second DCC delay chain, a DCC phase discriminator and a DCC logical control circuit, wherein the first DCC delay chain is used for receiving first clock signals and generating second clock signals; the second DCC delay chain is used for receiving the second clock signals and generating third clock signals; the DCC phase discriminator is used for receiving the first clock signals and the third clock signals and outputting signals for increasing or reducing lengths of the delay chains through phase comparison; and the DCC logical control circuit is used for receiving the signals for increasing or reducing the lengths of the delay chains and controlling the first DCC delay chain or the second DCC delay chain respectively. According to the correcting circuit, the technical problems that control methods of existing clock duty-ratio correcting circuits are too large in overshooting and jittering are solved, and both the overshooting and the jittering are reduced.