Efficient Techniques for Automatic Verification-Oriented Test Set Optimization

Most Systems-on-a-Chips include a custom microprocessor core, and time and resource constraints make the design of such devices a challenging task. This paper presents a simulation-based methodology for the automatic completion and refinement of verification test sets. The approach extends the μGP, an evolutionary test program generator, with the possibility to enhance existing test sets. Already devised test programs are not merely included in the new set, but assimilated and used as a starting point for a new test-program cultivation task. Reusing existing material cuts down the time required to generate a verification test set during the microprocessor design. Experimental results are reported on a small pipelined microprocessor, and show the effectiveness of the approach. Additionally, the use of the proposed methodology enabled to experimentally analyze the relationship of the different code coverage metrics used in the test program generation

[1]  Vishwani D. Agrawal,et al.  Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits [Book Review] , 2000, IEEE Circuits and Devices Magazine.

[2]  John Paul Shen,et al.  Superscalar processor validation at the microarchitecture level , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

[3]  Andrew Piziali,et al.  Functional verification coverage measurement and analysis , 2004 .

[4]  Jeffrey E. F. Friedl.  Mastering Regular Expressions , 1997 .

[5]  David A. Patterson,et al.  Computer architecture (2nd ed.): a quantitative approach , 1996 .

[6]  Richard M. Friedberg,et al.  A Learning Machine: Part I , 1958, IBM J. Res. Dev..

[7]  Kurt Keutzer,et al.  Coverage Metrics for Functional Validation of Hardware Designs , 2001, IEEE Des. Test Comput..

[8]  David R. Kaeli,et al.  The DLX instruction set architecture handbook , 1995 .

[9]  Chien-Nan Jimmy Liu,et al.  A novel approach for functional coverage measurement in HDL , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[10]  J. R. Heath,et al.  Methodology for synthesis, testing, and verification of pipelined architecture processors from behavioral-level-only HDL code and a case study example , 2001, Proceedings. IEEE SoutheastCon 2001 (Cat. No.01CH37208).

[11]  Giovanni Squillero,et al.  MicroGP—An Evolutionary Assembly Program Generator , 2005, Genetic Programming and Evolvable Machines.

[12]  Giovanni Squillero,et al.  Code Generation for Functional Validation of Pipelined Microprocessors , 2004, J. Electron. Test..

[13]  Jian Shen,et al.  Native mode functional test generation for processors with applications to self test and design validation , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[14]  Giovanni Squillero,et al.  Automatic test program generation: a case study , 2004, IEEE Design & Test of Computers.

[15]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .