An Effective Power-Aware At-Speed Test Methodology for IP Qualification and Characterization
暂无分享,去创建一个
Arnaud Virazel | Patrick Girard | Pankaj Agarwal | Kapil Juneja | Darayus Adil Patel | Sylvie Naudet | Balwant Singh | Rajesh Kumar Immadi
[1] Martin Radetzki,et al. IPQ: IP qualification for efficient system design , 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).
[2] Nur A. Touba,et al. Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains , 2010, 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems.
[3] Irith Pomeranz,et al. Techniques for minimizing power dissipation in scan and combinational circuits during test application , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[4] Hermann Fischer,et al. At-speed testing of SOC ICs , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[5] A. Arulmurugan,et al. Survey of low power testing of VLSI circuits , 2012, 2012 International Conference on Computer Communication and Informatics.
[6] Li-Wei Wang,et al. Quality and reliability of digital soft IP core and a qualification framework , 2011, 2011 International Conference on Quality, Reliability, Risk, Maintenance, and Safety Engineering.
[7] Mark Mohammad Tehranipoor,et al. Test-Pattern Grading and Pattern Selection for Small-Delay Defects , 2008, 26th IEEE VLSI Test Symposium (vts 2008).
[8] Sandeep K. Gupta,et al. DS-LFSR: a new BIST TPG for low heat dissipation , 1997, Proceedings International Test Conference 1997.
[9] Srivaths Ravi,et al. Power-aware test: Challenges and solutions , 2007, 2007 IEEE International Test Conference.
[10] Sherief Reda. Thermal and Power Characterization of Real Computing Devices , 2011, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.
[11] Kenneth M. Butler,et al. A case study of ir-drop in structured at-speed testing , 2003, International Test Conference, 2003. Proceedings. ITC 2003..
[12] R. Nelson. The last byte - Yet another thiotimoline application , 2002, IEEE Design & Test of Computers.
[13] Kwang-Ting Cheng,et al. Critical path selection for delay fault testing based upon a statistical timing model , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[14] Wolfgang Rosenstiel,et al. Measurement of IP qualification costs and benefits , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[15] Patrick Girard,et al. A modified clock scheme for a low power BIST test pattern generator , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.
[16] Takaki Yoshida,et al. A new approach for low-power scan testing , 2003, International Test Conference, 2003. Proceedings. ITC 2003..
[17] Akhil Garg,et al. State of the art low capture power methodology , 2011, 2011 IEEE International Test Conference.
[18] Janusz Rajski,et al. High-frequency, at-speed scan testing , 2003, IEEE Design & Test of Computers.
[19] James Tschanz,et al. Parameter variations and impact on circuits and microarchitecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[20] Michael S. Hsiao,et al. Peak power estimation of VLSI circuits: new peak power measures , 2000, IEEE Trans. Very Large Scale Integr. Syst..
[21] O. Rozeau,et al. 28nm FDSOI technology platform for high-speed low-voltage digital applications , 2012, 2012 Symposium on VLSI Technology (VLSIT).
[22] Vivek Chickermane,et al. Capture power reduction using clock gating aware test generation , 2009, 2009 International Test Conference.
[23] Eric Lindbloom,et al. Transition Fault Simulation , 1987, IEEE Design & Test of Computers.
[24] Krishnendu Chakrabarty,et al. Power Management for Wafer-Level Test During Burn-In , 2008, 2008 17th Asian Test Symposium.
[25] Jinjun Xiong,et al. Variation-aware performance verification using at-speed structural test and statistical timing , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.
[26] Lee Whetsel,et al. Adapting scan architectures for low power operation , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).
[27] Xiaoqing Wen,et al. Embedded Tutorial on Low Power Test , 2007, 12th IEEE European Test Symposium (ETS'07).
[28] Nandakumar Nityananda Tendolkar. Analysis of Timing Failures Due to Random AC Defects in VLSI Modules , 1985, DAC 1985.
[29] H. Onodera. Variability modeling and impact on design , 2008, 2008 IEEE International Electron Devices Meeting.
[30] C. P. Ravikumar,et al. At-speed transition fault testing with low speed scan enable , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).
[31] Alfred L. Crouch,et al. Design-For-Test For Digital IC's and Embedded Core Systems , 1999 .
[32] Akshay Gupta,et al. Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis , 2006, 2006 IEEE International Test Conference.
[33] R.-P. Vollertsen,et al. Burn-in discussion group minutes , 2000, 2000 IEEE International Integrated Reliability Workshop Final Report (Cat. No.00TH8515).
[34] Franziska Frankfurter,et al. Power Aware Testing And Test Strategies For Low Power Devices , 2016 .
[35] Kaushik Roy,et al. Test challenges for deep sub-micron technologies , 2000, Proceedings - Design Automation Conference.
[36] Atul Patel,et al. Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).
[37] S. Pravossoudovitch,et al. A gated clock scheme for low power scan testing of logic ICs or embedded cores , 2001, Proceedings 10th Asian Test Symposium.