Testability metrics for synthesis of self-testable designs and effective test plans

We propose a set of unified metrics for self-testability which are portable across different phases of synthesis. Furthermore, applicability of the proposed test metrics is verified through extensive experiments on benchmark designs.

[1]  Daniel G. Saab,et al.  Beta: behavioral testability analysis , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[2]  Minh N. Do,et al.  Youn-Long Steve Lin , 1992 .

[3]  Alex Orailoglu,et al.  SYNCBIST: SYNthesis for concurrent built-in self-testability , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[4]  Jacob A. Abraham,et al.  An easily computed functional level testability measure , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[5]  Alex Orailoglu,et al.  Test path generation and test scheduling for self-testable designs , 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

[6]  Christos A. Papachristou,et al.  A design for testability scheme with applications to data path synthesis , 1991, 28th ACM/IEEE Design Automation Conference.

[7]  Alex Orailoglu,et al.  Fine-grained concurrency in test scheduling for partial-intrusion BIST , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[8]  Reinaldo A. Bergamaschi,et al.  The effects of false paths in high-level synthesis , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[9]  Daniel D. Gajski,et al.  High ― Level Synthesis: Introduction to Chip and System Design , 1992 .

[10]  Alex Orailoglu,et al.  Microarchitectural Synthesis of VLSI Designs with High Test Concurrency , 1994, 31st Design Automation Conference.