Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests

We classify all path-delay faults of a combinational circuit intothree categories: singly-testable (ST), multiply-testable (MT), and singly-testable dependent} (ST-dependent). The classification uses anyunaltered single stuck-at fault test generation tool. Only two runsof this tool on a model network derived from the original network areperformed. As a by-product of this process, we generate single andmultiple input change delay tests for all testable faults. With thesetests, we expect that most defective circuits are identified. All STfaults are guaranteed detection in the case of a single fault, andsome may be guaranteed detection through robust and validatablenon-robust tests even in the case of multiple faults. An ST-dependentfault can affect the circuit speed only if certain ST faults arepresent. Thus, if all ST faults are tested, the ST-dependent faultsneed not be tested. MT faults cannot be guaranteed detection, butaffect the speed only if delay faults simultaneously exist on a setof paths, none of which is ST. Examples and results on several ISCAS‘89 benchmarks are presented. The method of classification throughtest generation using a model network is complex and can be appliedto circuits of moderate size. For larger circuits, alternativemethods will have to be explored in the future.

[1]  Douglas B. Armstrong,et al.  On Finding a Nearly Minimal Set of Fault Detection Tests for Combinational Logic Nets , 1966, IEEE Trans. Electron. Comput..

[2]  Sharad Malik,et al.  Delay computation in combinational logic circuits: theory and algorithms , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[3]  Sudhakar M. Reddy,et al.  On Delay Fault Testing in Logic Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Michael H. Schulz,et al.  DYNAMITE: an efficient automatic test pattern generation system for path delay faults , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Kwang-Ting Cheng,et al.  Generation of High Quality Tests for Robustly Untestable Path Delay Faults , 1996, IEEE Trans. Computers.

[6]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[7]  Vishwani D. Agrawal,et al.  Delay fault models and test generation for random logic sequential circuits , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[8]  Sudhakar M. Reddy,et al.  Fast Identification of Robust Dependent Path Delay Faults , 1995, 32nd Design Automation Conference.

[9]  Michael L. Bushnell,et al.  EST: The new frontier in automatic test-pattern generation , 1990, DAC '90.

[10]  Robert K. Brayton,et al.  Timed Boolean functions - a unified formalism for exact timing analysis , 1994, The Kluwer international series in engineering and computer science.

[11]  Robert K. Brayton,et al.  Equivalence of robust delay-fault and single stuck-fault test generation , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[12]  Robert K. Brayton,et al.  Delay Fault Coverage and Performance Tradeoffs , 1993, 30th ACM/IEEE Design Automation Conference.

[13]  Vishwani D. Agrawal,et al.  Energy models for delay testing , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Vishwani D. Agrawal,et al.  Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[15]  Premachandran R. Menon,et al.  Synthesis of Delay-Verifiable Combinational Circuits , 1995, IEEE Trans. Computers.

[16]  A. J. Strojwas,et al.  Primitive path delay fault identification , 1997 .

[17]  Vishwani D. Agrawal,et al.  Logic systems for path delay test generation , 1993, Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference.

[18]  Kwang-Ting Cheng,et al.  Classification and identification of nonrobust untestable path delay faults , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Prathima Agrawal,et al.  Test Generation for Path Delay Faults Using Binary Decision Diagrams , 1995, IEEE Trans. Computers.

[20]  Edward J. McCluskey,et al.  Transients in combinational logic circuits , 1962 .

[21]  Gordon L. Smith,et al.  Model for Delay Faults Based upon Paths , 1985, ITC.

[22]  Michael L. Bushnell,et al.  Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming , 1995, Proceedings 13th IEEE VLSI Test Symposium.