Phase change memory device

A phase change memory device is provided to hierarchically drive word lines according to a main word line signal and a sub word line signal, thereby maximizing current sink capability. A cell array(100) comprises plural unit phase change resistance cells. The unit phase change resistance cells are arranged in cross domains of word lines and bit lines. Plural sub word line drivers(110,120) drive the word lines according to sub word line signals. The plural sub word line drivers drive selected word lines with a first voltage. The plural sub word line drivers drive the rest of the word lines with a second voltage. Main word line drivers(130,140) drive the sub word line drivers according to a main word line signal.