Efficient testability enhancement for combinational circuit
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[1] Arthur D. Friedman,et al. Test Point Placement to Simplify Fault Detection , 1974, IEEE Transactions on Computers.
[2] Elizabeth M. Rudnick,et al. An observability enhancement approach for improved testability and at-speed test , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[3] Gary S. Ditlow,et al. Random Pattern Testability , 1984, IEEE Transactions on Computers.
[4] Eric Lindbloom,et al. Random-Pattern Coverage Enhancement and Diagnosis for LSSD Logic Self-Test , 1983, IBM J. Res. Dev..
[5] Edward J. McCluskey,et al. Probabilistic Treatment of General Combinational Networks , 1975, IEEE Transactions on Computers.
[6] Janak H. Patel,et al. Experimental evaluation of testability measures for test generation (logic circuits) , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[7] Daniel Brand,et al. Synthesis of pseudo-random pattern testable designs , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.
[8] Melvin A. Breuer,et al. Digital systems testing and testable design , 1990 .
[9] Jacob Savir,et al. On Random Pattern Test Length , 1984, IEEE Transactions on Computers.
[10] Balakrishnan Krishnamurthy. A Dynamic Programming Approach to the Test Point Insertion Problem , 1987, 24th ACM/IEEE Design Automation Conference.