A High-Speed HUFFMAN Decoding Circuit
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This paper presents a circuit of high-speed HUFFMAN decoding operation by studying the characteristic of the decoding tables and simplifying algorithm of decoding . It takes much smaller memory in size and the decoding becomes significant faster. The design has been implemented on FPGA (Altera EP1S10F780C6 ) and it can run stably at the speed of 100 MHz with high output bandwidth (about 1.0Gbits/sec average).