An ABR rate-based congestion control algorithm for ATM switches with per-VC queueing

The support of available bit rate (ABR) service in ATM networks has been extensively studied in literature under the assumption that all ABR traffic is queued in the switches in a common first-in-first-out (FIFO) queue. In this context, which models what is typically done in current generation switches, the central issue has been the design of ABR schemes for the switch behavior that are able to allocate an accurate fair share of available bandwidth to each ABR virtual connection (VC). The new generation of switches that will soon be deployed, however, provides per-VC queueing and scheduling to multiplex traffic from different VC's. In this paper, we show how the ABR scheme used in the switches can take advantage of the new queueing and scheduling capabilities. Since the per-VC scheduler itself is able to provide flow isolation and fair service to the VC's, the ABR scheme is not required to accurately compute the fair share, but can focus primarily on queue control. Thus, a simple ABR scheme that only uses an approximation of the fair share is sufficient to achieve excellent performance. Following these principles, we present a new algorithm, called the enhanced dynamic max rate control algorithm (EDMRCA), which is the extension to per-VC queueing of DMRCA, a simple queue-length-based algorithm developed for common-FIFO queueing. EDMRCA does not suffer the problems of its common-FIFO counterpart in allocating the fair share when ABR traffic interferes with highly-bursty traffic and in other demanding traffic scenarios, and inherits the robustness and excellent congestion control properties of DMRCA. EDMRCA achieves fairness at least comparable with schemes using accurate computation of the fair share, offers superior queue control, and requires only a fraction of the complexity.