Reducing Write Latency by Integrating Advanced PreSET Technique and Two-Stage-Write with Inversion Schemes

The need for a memory with larger capacity is increasing to accommodate the high performance in computers. As this need grows, there is a very noticeable technology gap between the development in memory and processor. Currently, one popular area of research is to find new technology to improve the memory efficiency in one way or another. This research area is significant as memory is an essential component in any computer and it constantly needs improvement and upgrading. To address this issue, many studies are carried out on Phase Change Memory (PCM) that has a high potential to replace DRAM. In this paper, a new technique is studied and evaluated to enhance the overall performance by combining the PreSET technique and the Two-Stage-Write with inversion to reduce the write latency. This is achieved by pre-setting (set to 1) the dirty cache line beforehand and if the process fails, it shifts to Two-Stage-Write with inversion. The proposed technique reduces the running time of the write operation while keeping the power constrain into consideration. By exploring and obtaining results of the techniques stated above, the Two-Stage-Write and Two-Write-Stage with inversion have reduction on the read latency by average of 45.8% and 68.4%, respectively. The Two-Stage-Write, Two-Stage-Write with inversion and PreSET provided performance improvement over the baseline by 21.9%, 33.9% and 27.8%, respectively. Hence, the proposed technique showed a significant improvement.