Built-In Test Engine For Memory Test

In this paper we will present an on-chip method for testing high performance memory devices, that occupies minimal area and retains full flexibility. This is achieved through microcode test instructions and the associated on-chip state machine. In addition, the proposed methodology will enable at-speed testing of memory devices. The relevancy of this work is placed in context with an introduction to memory testing and the techniques and algorithms generally used today.

[1]  Marian Marinescu,et al.  Simple and Efficient Algorithms for Functional RAM Testing , 1982, ITC.

[2]  Sying-Jyan Wang,et al.  Efficient built-in self-test algorithm for memory , 2000, Proceedings of the Ninth Asian Test Symposium.

[3]  Ad J. van de Goor,et al.  Using March Tests to Test SRAMs , 1993, IEEE Des. Test Comput..

[4]  Sunil Shukla,et al.  A fault modeling technique to test memory BIST algorithms , 2002, Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002).

[5]  Sungju Park,et al.  A microcode-based memory BIST implementing modified march algorithm , 2001, Proceedings 10th Asian Test Symposium.

[6]  A. J. van de Goor,et al.  Testing Semiconductor Memories: Theory and Practice , 1998 .

[7]  Cheng-Wen Wu,et al.  Cost and benefit models for logic and memory BIST , 2000, DATE '00.

[8]  Howard Leo Kalter,et al.  Processor-based built-in self-test for embedded DRAM , 1998, IEEE J. Solid State Circuits.