A Capacitively Degenerated 100-dB Linear 20–150 MS/s Dynamic Amplifier

This paper presents a new dynamic residue amplifier topology for pipelined analog-to-digital converters. With an input signal of 100 mV<sub>pp,diff</sub> and 4<inline-formula> <tex-math notation="LaTeX">$\times$ </tex-math></inline-formula> gain, it achieves −100-dB total harmonic distortion, the lowest ever reported for a dynamic amplifier. Compared to the state of the art, it exhibits 25 dB better linearity with twice the output swing and similar noise performance. The key to this performance is a new linearization technique based on capacitive degeneration, which exploits the exponential voltage-to-current relationship of MOSFET in weak inversion. The prototype amplifier is fabricated in a 28-nm CMOS process and dissipates only 87 <inline-formula> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> at a clock speed of 43 MS/s, thereby improving the energy per cycle by 26<inline-formula> <tex-math notation="LaTeX">$\times$ </tex-math></inline-formula> compared with that of state-of-the-art high-linearity amplifiers.

[1]  Frank M. L. van der Goes,et al.  A 66 dB SNDR pipelined split-ADC using class-AB residue amplifier with analog gain correction , 2015, ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC).

[2]  P.J. Hurst,et al.  A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration , 2004, IEEE Journal of Solid-State Circuits.

[3]  J. Kornblum,et al.  A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter , 2006, IEEE Journal of Solid-State Circuits.

[4]  Kazuki Sobue,et al.  Ring amplifiers for switched-capacitor circuits , 2012, 2012 IEEE International Solid-State Circuits Conference.

[5]  Frank M. L. van der Goes,et al.  A 12 b 53 mW 195 MS/s Pipeline ADC with 82 dB SFDR Using Split-ADC Calibration , 2015, IEEE Journal of Solid-State Circuits.

[6]  Boris Murmann,et al.  A 12-bit, 200-MS/s, 11.5-mW pipeline ADC using a pulsed bucket brigade front-end , 2013, 2013 Symposium on VLSI Circuits.

[7]  J. Mitola,et al.  Software radios: Survey, critical evaluation and future directions , 1992, IEEE Aerospace and Electronic Systems Magazine.

[8]  E. Iroaga,et al.  A 12-Bit 75-MS/s Pipelined ADC Using Incomplete Settling , 2007, IEEE Journal of Solid-State Circuits.

[9]  Han Yan,et al.  A 1.5 mW 68 dB SNDR 80 Ms/s 2 $\times$ Interleaved Pipelined SAR ADC in 28 nm CMOS , 2014, IEEE Journal of Solid-State Circuits.

[10]  Koichi Hamashita,et al.  A 14b 60 MS/s Pipelined ADC Adaptively Cancelling Opamp Gain and Nonlinearity , 2014, IEEE Journal of Solid-State Circuits.

[11]  Yong-Bin Kim,et al.  Noise Reduction Technique Through Bandwidth Switching for Switched-Capacitor Amplifier , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  Christian Enz,et al.  CMOS low-power analog circuit design , 1996, Emerging Technologies: Designing Low Power Digital Systems.

[13]  B. Murmann,et al.  A 12 b 75 MS/s pipelined ADC using open-loop residue amplification , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[14]  Jan Craninckx,et al.  A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS , 2012, IEEE Journal of Solid-State Circuits.

[15]  Boris Murmann,et al.  A 12-bit, 30-MS/s, 2.95-mW pipelined ADC using single-stage class-AB amplifiers and deterministic background calibration , 2010, 2010 Proceedings of ESSCIRC.

[16]  David A. Johns,et al.  A Low-Power Capacitive Charge Pump Based Pipelined ADC , 2010, IEEE Journal of Solid-State Circuits.

[17]  Ian Galton,et al.  A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction , 2009, IEEE Journal of Solid-State Circuits.

[18]  Jieh-Tsorng Wu,et al.  A CMOS 33-mW 100-MHz 80-dB SFDR sample-and-hold amplifier , 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

[19]  Hae-Seung Lee,et al.  A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC , 2009, IEEE Journal of Solid-State Circuits.

[20]  B. Murmann,et al.  A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC Using Dynamic Source Follower Residue Amplification , 2009, IEEE Journal of Solid-State Circuits.

[21]  Akira Matsuzawa,et al.  A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers , 2016, IEEE Journal of Solid-State Circuits.

[22]  Jan Craninckx,et al.  A 1.7mW 11b 250MS/s 2× interleaved fully dynamic pipelined SAR ADC in 40nm digital CMOS , 2012, 2012 IEEE International Solid-State Circuits Conference.

[23]  Francois Krummenacher,et al.  A 4-MHz CMOS Continuous-Time Filter with On-Chip Automatic Tuning , 1987, ESSCIRC '87: 13th European Solid-State Circuits Conference.

[24]  Dong Wang,et al.  An Integrator-Based Pipelined ADC With Digital Calibration , 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.