Systematic design of digital algorithms for synchronization: from theory to VLSI

A methodology for the design and implementation of digital synchronization algorithms is discussed. Estimation theory is employed in the first step to systematically derive structures. Next, the performance of design alternatives is evaluated taking quantization and discretization into account. In the third step the algorithms are mapped onto a suitable processor architecture. The necessity for integrated simulation tools ranging from system level to the VLSI/DSP (digital signal processor) level in this highly interactive design process is emphasized. A design example involving DIRECS (Digital-Receiver Chip Set) is presented.<<ETX>>

[1]  Pooi Kam,et al.  An Adaptive Receiver with Memory for Slowly Fading Channels , 1984, IEEE Trans. Commun..

[2]  K. Mueller,et al.  Timing Recovery in Digital Synchronous Data Receivers , 1976, IEEE Trans. Commun..

[3]  Roland E. Best.  Phase-Locked Loops , 1984 .

[4]  Floyd M. Gardner,et al.  Phaselock techniques , 1984, IEEE Transactions on Systems, Man, and Cybernetics.

[5]  Miodrag Potkonjak,et al.  Fast prototyping of datapath-intensive architectures , 1991, IEEE Design & Test of Computers.

[6]  Heinrich Meyr,et al.  A systematic approach to carrier recovery and detection of digitally phase modulated signals of fading channels , 1989, IEEE Trans. Commun..

[7]  Hugo De Man,et al.  Architecture-driven synthesis techniques for VLSI implementation of DSP algorithms , 1990, Proc. IEEE.

[8]  Gerhard Fettweis.  New rotationally invariant trellis codes for 8PSK modulation , 1989, IEEE International Conference on Communications, World Prosperity Through Communications,.

[9]  Heinrich Meyr,et al.  Synchronization in digital communications , 1990 .

[10]  H. Meyr,et al.  An investigation of channel estimation and equalization techniques for moderately rapid fading HF-channels , 1991, ICC 91 International Conference on Communications Conference Record.

[11]  Heinrich Meyr,et al.  Digital filter and square timing recovery , 1988, IEEE Trans. Commun..

[12]  Heinrich Meyr,et al.  VLSI implementation of synchronization algorithms in a 100 Mbit/s digital receiver , 1990, [Proceedings] GLOBECOM '90: IEEE Global Telecommunications Conference and Exhibition.

[13]  Gerd Ascheid,et al.  A new method for phase synchronization and automatic gain control of linearly modulated signals on frequency-flat fading channels , 1991, IEEE Trans. Commun..

[14]  John H. Lodge,et al.  TCMP-a modulation and coding strategy for Rician fading channels , 1989, IEEE J. Sel. Areas Commun..

[15]  Seymour Stein,et al.  Fading Channel Issues in System Engineering , 1987, IEEE J. Sel. Areas Commun..

[16]  C. Rapp.  Coded and uncoded M-PSK and CPM signals on nonlinear bandpass channels: an approach to a fair comparison , 1990, [Proceedings] GLOBECOM '90: IEEE Global Telecommunications Conference and Exhibition.