VLSI Placement Using Quadratic Programming and Network Partitioning Techniques

Abstract VLSI cell placement involves positioning cells within a target placement geometry while minimizing the interconnecting wire length and placement area. In this paper, the placement problem is solved using a combination of quadratic programming, circuit partitioning, clustering and greedy cell interchange heuristics. The solution of a sequence of quadratic programs and circuit partitioning problems provides the general positions of cells in a high quality placement. Computational efficiency is achieved by using an interior point method for solving the sequence of quadratic programs. A very efficient clustering heuristic is used to keep important groups of cells together as the cells are spread throughout the placement area. Numerical results on a set of benchmark circuits illustrate that this new approach produces standard cell placements that are up to 17% better in wire length, 14% better in row length and up to 24 times faster than a well known Simulated Annealing placement heuristic.

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