Improving the Performance of the Carrier Tracking Loop for GPS Receivers in Presence of Transient Errors due to PVT Variations

The increase in integration density and the require-ment of low power supplies to reduce energy consumption canmake circuits more and more sensitive to upsets errors. Theloss of robustness increases with process/voltage and temperature(PVT) variations. This paper shows that the impact of errorsthat appear when computing the estimation of the Doppleroffsets in a GPS application can be greatly reduced by tuningappropriately the carrier filter bandwidth. The effectiveness ofthe proposed was proven by comparing the performance a faultyGPS receiver to a non-faulty (noisy-free) GPS receiver at twolevels: the standard deviation of the tracking error variance(by theory and by simulation) as well as the standard deviationbetween positions given by the faulty (noisy) and non-faulty (thenoiseless) GPS receivers. Modifying properly the optimal filterbandwidth values gives astonishing results in terms of robustnessagainst errors. The modification of the bandwidth filter valuesintroduces almost no position degradation in a noise-free GPSreceiver (only11cm in average). With 40 % of error, the standarddeviation of the error in the position does not exceed 2 m byincreasing the PLL bandwidth while the tracking loop does notsupport more than 6% of errors.

[1]  Emmanuel Boutillon,et al.  Reliable gold code generators for GPS receivers , 2015, 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS).

[2]  Emmanuel Boutillon,et al.  Reducing the impact of internal upsets inside the correlation process in GPS Receivers , 2015, 2015 Conference on Design and Architectures for Signal and Image Processing (DASIP).

[3]  Ahmed M. Kamel Design and Testing of an Intelligent GPS Tracking Loop for Noise Reduction and High Dynamics Applications , 2010 .

[4]  Norbert Wehn,et al.  A Cross-Layer Reliability Design Methodology for Efficient, Dependable Wireless Receivers , 2014, ACM Trans. Embed. Comput. Syst..

[5]  V. Rich Personal communication , 1989, Nature.

[6]  James B. Y. Tsui,et al.  Fundamentals of global positioning system receivers , 2000 .

[7]  Bashir M. Al-Hashimi,et al.  Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks , 2007 .

[8]  Trevor Mudge,et al.  Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[9]  Robert C. Aitken,et al.  TIMBER: Time borrowing and error relaying for online timing error resilience , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[10]  Yi Luo,et al.  An Error Correction Method for Binary and Multiple-Valued Logic , 2011, 2011 41st IEEE International Symposium on Multiple-Valued Logic.

[11]  Valentin Gherman,et al.  System-level hardware-based protection of memories against soft-errors , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[12]  Michael Nicolaidis Double-sampling architectures , 2014, 2014 IEEE International Reliability Physics Symposium.

[13]  Emmanuel Boutillon,et al.  Reliable NCO carrier generators for GPS receivers , 2015, 2015 Conference on Design and Architectures for Signal and Image Processing (DASIP).

[14]  Bashir M. Al-Hashimi,et al.  Joint Consideration of Fault-Tolerance, Energy-Efficiency and Performance in On-Chip Networks , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[15]  David Blaauw,et al.  Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation , 2003, MICRO.

[16]  Naresh R. Shanbhag,et al.  Energy-efficient signal processing via algorithmic noise-tolerance , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[17]  Sarita V. Adve,et al.  The impact of technology scaling on lifetime reliability , 2004, International Conference on Dependable Systems and Networks, 2004.

[18]  James T. Curran,et al.  Improving the Design of Frequency Lock Loops for GNSS Receivers , 2012, IEEE Transactions on Aerospace and Electronic Systems.